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October 2005

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Subject:
From:
Phil Nutting <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Phil Nutting <[log in to unmask]>
Date:
Thu, 6 Oct 2005 12:39:26 -0400
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And in some cases we have found that routing a slot in the board between traces is the most effective way to cram more stuff in a smaller package and still pass Hipot testing and TÜV creepage and clearance requirements. 

Phil

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Brooks,Bill
Sent: Thursday, October 06, 2005 12:02 PM
To: [log in to unmask]
Subject: Re: [TN] Highvoltage testvoltage

Marcel,

That particular section of the IPC-2221 spec refers to the insulation
resistance across the surface and through the board material. If you are
planning on passing a test with 2100 volts peak to peak you need to
calculate a minimum spacing something like this to pass.

For internal conductors - .25mm plus 4mm = 4.25mm plus mfg tolerance
For external conductors uncoated, sea level to 3050m - 2.5mm plus 8mm =
10.5mm plus mfg tolerance

And so on... Just find the condition that you expect the board to survive in
and make sure that your spacing between conductors is greater than the
minimum number you come up with by calculating the voltage spacing from that
table. In your case the minimum spacing on the outside surfaces would be
10.5mm. If you expect to meet that minimum, you mist add the manufacturing
tolerances into your equation before coming up with the nominal spacing you
will design the board with...

I would design based upon passing the test voltage, otherwise you will not
pass the test and designing to the 'working' voltage doesn't help you.

Note that the conformal coatings can reduce the spacing needed, however they
indicate that you should not depend upon the coatings as a way to prevent
voltage breakdown, obviously the coatings are not reliable under all
circumstances as an insulator and the coating thickness varies greatly...
they only protect the surface of the board and components from contamination
from dirt, humidity and/or any conductive materials in the environment being
deposited between the two voltage extremes and providing an ionic path for
voltage break over.

Avoid sharp corners on traces or pads or features in copper in between the 2
voltage extremes... electrical arcing tends to form at the sharp points...
Clean boards have a much better chance of passing the electrical test, once
an ionic path has formed through any contamination... it's all over.

Note that these are minimum spacings... If you are trying to pass a safety
agency test, you may be required to use greater spacing to qualify. For
example TUV has more stringent requirements than the minimums stated in
Table 6-1 in IPC-2221.


Best regards,


Bill Brooks - KG6VVP
PCB Design Engineer, C.I.D.+, C.I.I.
Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510
Datron World Communications, Inc.
_______________________________________
San Diego Chapter of the IPC Designers Council
Communications Officer, Web Manager
http://dcchapters.ipc.org/SanDiego/
http://pcbwizards.com

-----Original Message-----
From: Marcel van den Berk [mailto:[log in to unmask]]
Sent: Thursday, October 06, 2005 4:58 AM
To: [log in to unmask]
Subject: [TN] Highvoltage testvoltage

Dear Technet-ers,

We, at development ASML, have some discussions and questions about the
interpretation of chapter 6.3 electrical clearances and in particular
for highvoltage (700Vac).

Question regarding to IPC-2221 :
1) Are the electrical conductor spacings as mentioned in table 6-1 based
on a testvoltages ? (for example 2100V testvoltage)
2) Must  i design , my board, on the testvoltage (2100V) or on the
working voltage ?
3) Is there a relationship between IPC-2221, 6.3 and the IEC60950 ? and
if "yes" where can i find this relationship?
4) Can i use the same highvoltage rules for Flex-boards?

Is there anyone how can help me? , thanks in advance.

Best Regards,
------------------------------------------------------------------------
----
Marcel van den Berk
DFM Support / PCB Technology / Board layout
Electronic DEVelopment------------PRoduction Standards group

A.S.M.L.
De Run 6665
p.o.box 324
5504 DT Veldhoven
The Netherlands

E-mail:        [log in to unmask]
Internet:      http://www.asml.com <http://www.asml.com/>
------------------------------------------------------------------------
----




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