Mumtaz
If I'm interpreting the cross sections correctly, you have a 4-layer buried
via structure. The vias in this sub-part were filled with something prior to
adding foil caps with a single-ply of a thin prepreg or maybe RCC. But the
buried vias were not plated over prior to lamination.
From the photos (I'm arbitrarily calling the top layer in each photo layer
1):
Blister 1 and Blister 2 show separation between the layer 1/2 dielectric and
layer 2. Blister 1 also shows delamination under layer 2 but I think I also
see remnants of layer 1 to 2 microvias, so I'm thinking the failure on both
samples is along the layer 2 interface. On blister 1 the microvias held
this opening together well enough that the separation under layer 2 was the
next weakest point but the original failure is along layer 2.
I don't see anything wrong with After Bake 1, but After bake 2 photo looks
like it still has delamination along the bottom of layer 5. Of course, the
bottom of layer 5 is the same as the top of layer 2 if the samples/photos
have been flipped.
Obviously this delamination is not a good sign.
As for the partially effective "corrective action" baking would address two
possible causes. You've mentioned the first: undercure. The other is
entrapped moisture. I'd be surprised if you are looking at undercure here.
For one, your fabricator ought to be able to explain why the parts didn't
get cured properly. And I wouldn't expect undercure to exhibit an
"explosive" failure with enough force to the delamination.
That leaves moisture. I think you have two likely causes for this. If any
of the vias did not get filled properly, they could have retained water
which expanded explosively during reflow. This would be very consistent
with the delamination propogating along the layer 2 (or 5) interface since
the moisture would push against the prepreg/RCC.
The other mechanism for moisture would be that the prepreg/RCC used to bond
the foil caps was inadequate to fill in the circuitry on layers 2 and 5. If
so, you'd get lamination voids in these openings. If these were then
drilled through this allowed chemistry from post-drilling operations to
enter this opening. This mechanism has a higher probability of occurring if
the outer dielectrics are RCC since that would explain why the failure
appears limited to layers 2 and 5. If prepreg, you'd expect failures on
both sides of these openings.
Regardless, I don't think you can use these but I hope this helps determine
the root cause and path forward. Baking perhaps moved some of moisture
around, diffusing into and perhaps out of the board but there's still
probably residual moisture there as well as entrapped ionic contamination.
By the way, you may want to ask your fabricator if they had excessive
fallout for IL shorts at electrical test. If so, the likely mechanism is
lamination voids. If not, I'd go with unfilled buried vias.
Good Luck!
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Mumtaz Bora
Sent: Thursday, September 15, 2005 6:21 PM
To: [log in to unmask]
Subject: [TN] Rework for Delaminated PWBs
Dear Technetters,
We have received a large batch of PWBs that is showing delamination after
reflow at peak temp. 230C. Laminate is high Tg - 170C.
Supplier is proposing to perform the following rework -- on these boards
instead of providing replacement parts.
Oven bake at 190C for 2.5 hours followed by second bake at 150C for 2
hours at 6kg/cm2 pressure. Will this guarantee a full cure?
I am concerned about latent failures and layers opening up as full cure was
not achieved the first time.
Any inputs from the forum will be appreciated.
I will request Steven Gregory to place the image of delamination on his
website. Have a great weekend.
Thank-you
Mumtaz
D/ 252 - SMT Process and Component Quality
Bldg. V238E
Voice (858)-882-1967
Fax (858)-882-3126
Page (858)-635-1180
Cell: (858) -449-7054
email: [log in to unmask]
Kyocera-Wireless Corp.
10300, Campus Point Drive
---------------------------------------------------
Technet Mail List provided as a service by IPC using LISTSERV 1.8e
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt or (re-start) delivery of Technet send e-mail to
[log in to unmask]: SET Technet NOMAIL or (MAIL)
To receive ONE mailing per day of all the posts: send e-mail to
[log in to unmask]: SET Technet Digest
Search the archives of previous posts at: http://listserv.ipc.org/archives
Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16
for additional information, or contact Keach Sasamori at [log in to unmask] or
847-615-7100 ext.2815
-----------------------------------------------------
San Diego, Ca 92121,USA
---------------------------------------------------
Technet Mail List provided as a service by IPC using LISTSERV 1.8e
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL)
To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest
Search the archives of previous posts at: http://listserv.ipc.org/archives
Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815
-----------------------------------------------------
|
