Yep, all the bumps are blind vias...
Kind regards,
-Steve Gregory-
Senior Process Engineer
LaBarge Incorporated
Tulsa, Oklahoma
(918) 459-2285
(918) 459-2350 FAX
Franklin Asbell <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
09/13/2005 09:47 AM
Please respond to TechNet E-Mail Forum <[log in to unmask]>; Please respond to Franklin Asbell <[log in to unmask]>
To: [log in to unmask]@SMTP@Exchange
cc: (bcc: Stephen R Gregory/LABARGE)
Subject: Re: [TN] raised vias...
A couple more questions then...the vias with bumps, are those all blind
vias?
I would not think that this would be caused strictly by solder fill, looks
too uniform, something else is the catalyst, I would think the HASL process
would make these into depressions...unless something is preventing the
removal of solder in those areas, or, the solder is covering conformally,
another base...copper perhaps? Then why is there a copper bump?
Cross section will probably give a better picture.
Franklin
-----Original Message-----
From: Steve Gregory [mailto:[log in to unmask]]
Sent: Tuesday, September 13, 2005 8:32 AM
To: [log in to unmask]
Subject: Re: [TN] raised vias...
Mornin' all you Technetters!
Just to go over things once again, this board
is a 10-layer board that has a .045" thick, solid
copper core in the center of it. It's made of IPC
4101/26 laminate (GF), the pre-preg is also IPC
4101/26 (PGF).
There's 1/2-ounce copper on layers 1,5,6, and
10, all the rest are to be 1-ounce. The drawing
doesn't call out for ANY hole fill.
There are 163 blind vias in this board. The drill
chart calls out for them to be .015" max.
When I first looked at the board, I mistakenly
thought that they were just solder bumps that
occured from the use of via-in-pad. I've seen
these bumps before. and not thought too much
about them.
When I started worrying, was when I observed
open holes and them not being covered with
solder.
But this time, our customer fed back to us that
the PowerPAK SO8 device (I have a drawing on
my web page of the device) was showing insufficient
solder defects, which to me would occur if the device
was being held above the board for some reason...I
used a 6-mil stencil to build the boards BTW.
We've shipped everything that we built. But I do
have one extra bare fab that wasn't built...that's where
the picture on my web page came from. I'm going
have a cross section done on it...because from the
feedback I'm getting from everyone, something isn't
right with this fab.
Kind regards,
-Steve Gregory-
Senior Process Engineer
LaBarge Incorporated
Tulsa, Oklahoma
(918) 459-2285
(918) 459-2350 FAX
|---------+---------------------------->
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| | Sent by: TechNet |
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| | |
| | 09/13/2005 07:41 |
| | AM |
| | Please respond to|
| | TechNet E-Mail |
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>---------------------------------------------------------------------------
-----------------------------------|
|
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| To: [log in to unmask]@SMTP@Exchange
|
| cc: (bcc: Stephen R Gregory/LABARGE)
|
| Subject: Re: [TN] raised vias...
|
>---------------------------------------------------------------------------
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What was the material used for fill?
See a couple issues,
1. Excessive fill
2. No planarization
Correct via fill usually requires planarization after fill to even the
surface, even though it appears that was not performed at all there seems
to
be an excessive amount of fill from the start.
I would also suspect from the appearance the presence of voids in the
filled
holes. Might be worth investigating.
Franklin
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Brooks,Bill
Sent: Monday, September 12, 2005 5:54 PM
To: [log in to unmask]
Subject: [TN] raised vias...
Can someone give us a read on what they think cause the raised vias on
Steve's website picture? http://www.stevezeva.homestead.com page 2.
Bill Brooks - KG6VVP
PCB Design Engineer, C.I.D.+, C.I.I.
Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510
Datron World Communications, Inc.
_______________________________________
San Diego Chapter of the IPC Designers Council
Communications Officer, Web Manager
http://dcchapters.ipc.org/SanDiego/
http://pcbwizards.com
-----Original Message-----
From: Steve Gregory [mailto:[log in to unmask]]
Sent: Monday, September 12, 2005 2:28 PM
To: [log in to unmask]
Subject: Re: [DC] Raised vias
Hi Fred and Everybody!
Speaking of "Raised Vias" and "Anthills", I have some anthills on some
Boards that we're building here now.
The anthills aren't from plugging or anything, but are blind via in pad.
I thought that they wouldn't present too much of a problem because I
thought that after printing paste and reflow, everything would level
out...but that wasn't the case.
At locations where I was placing something called a PowerPAK SO8, there
was
open solder defects at some of the joints because (I think) of the
raised
vias. You can see the PowerPAK part drawing, and the raised vias that
I'm
talking about on my web page at: http://www.stevezeva.homestead.com . Go
to
"Picture Page 2" and look for "PowerPAK SO8 and Raised Vias".
I don't have a clue why the vias are raised like that...maybe that's a
question for the TechNet.
Kind regards,
-Steve Gregory-
Senior Process Engineer
LaBarge Incorporated
Tulsa, Oklahoma
(918) 459-2285
(918) 459-2350 FAX
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