IPC-600-6012 Archives

August 2005

IPC-600-6012@IPC.ORG

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From:
Karl Sauter <[log in to unmask]>
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Date:
Wed, 10 Aug 2005 10:54:40 -0700
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All

This is a good discussion on what the definitions of the terms/words
should be.  Clarifying the terms used should be helpful.

However recommend NOT relaxing any working industry requirements for how
many "thin spots" (below minimum copper thickness) can be present in
PTHs, etc.  Our IST studies show that below minimum PTH copper thickness
does have a significant impact on long term PTH via reliability.

Regards,
Karl Sauter
Sun Microsystems


Denny Cantwell wrote:
> To the group:
>
> I think that our industry "shot itself in the foot" when we all agreed
> to define "thin copper (less than xx% of required thickness) as a
> "VOID".  The criteria that we established, was that if we found a thin
> spot (void) in a microsection, then we would 100% visually inspect the
> lot of boards for voids.  Maybe its my advancing age and loss of visual
> acuity, but when I look into a hole in a board, even under the best
> scopes available, I cannot determine if there are areas of the hole wall
> that have .0007" thick copper (which is a void) from the rest of the
> hole wall that has .001" minimum thickness copper plating, and meets the
> specifications.  However, even with my bad eyes, I can see a void in a
> hole that is a "complete absence" of the required materials, be it
> copper plating, or final finish material.(Ni/Au, SnPb, etc)  I think
> that logic would require us to define voids as a complete absence of
> material, in keeping with Merriam Webster's definitions.  This is the
> criteria we use when we are looking at "laminate voids" "soldermask
> voids", or any of the myriad uses of the word void.  A "thin spot" in
> copper should never have been considered as a "void".  Personal
> opinion---everybody's got one.
>
> Dennis J. Cantwell
> R & D Liaison
> Printed Circuits, Inc.
> 1200 West 96th Street
> Minneapolis, MN 55431-2699
> 952-888-7900
> [log in to unmask]
>
>
> -----Original Message-----
> From: IPC-600-6012 [mailto:[log in to unmask]] On Behalf Of Reed,
> Randy
> Sent: Wednesday, August 10, 2005 10:45 AM
> To: [log in to unmask]
> Subject: Re: [IPC-600-6012] Request for Plating Definitions for IPC-T-50
>
> I offer the following for consideration for the definition of plating
> void.
>
> Plating Void: An isolated thinning of the copper plating thickness that
> is
> less than the minimum copper thickness limit.
>
> The reason I offer this alternate definition is the absence of plating
> does
> not make sense in the following scenario.
>
> "The customer specification states the minimum copper plate thickness is
> 0.0007" and the acceptable plating void quantity is 1 maximum.  On the
> microsection evaluated there is an isolated location where the copper
> thickness thinned to 0.0001".  This sample is unacceptable to the copper
> thickness limit and acceptable to the plating void limit.  The
> reliability
> of the sample is no different."
>
> Randy Reed
> Merix Corporation
>
> -----Original Message-----
> From: IPC-600-6012 [mailto:[log in to unmask]] On Behalf Of Susan
> Mansilla
> Sent: Wednesday, August 10, 2005 6:09 AM
> To: [log in to unmask]
> Subject: Re: [IPC-600-6012] Request for Plating Definitions for IPC-T-50
>
> Greetings to All
> I would offer the following definitions
>
> Plating Void - Complete Absence of Plating.  Some specifications have a
> minimum value that is considered to be a void in lieu of complete
> absence of
> plating.
>
> Plating Fold - Line that is visible after microetch in hole wall copper
> plating where the plating on two sides of a void plate up and eventually
> touch.
>
> Tangency - In a vertical microsection, the extreme degree of
> misregistration
> where there is any evidence of the original inner layer foil visible on
> one
> side of the hole.  No evidence of original innner layer foil would be
> considered to be misregistration to the point of breakout.
>
> Susan Mansilla
> Technical Director
> Robisan Laboratory, Inc
> 6502 E 21st Street
> Indianapolis, IN 46219
>
> 317-353-6249 phone
> 317-917-2379 fax
>
> www.robisan.com

--
Karl Sauter             Staff Engineer, Engineering Technologies
                        Sun Microsystems Inc.
                        Office: (650) 786-7663 / x87663
                        E-mail: [log in to unmask]

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