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July 2005

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Subject:
From:
Al Onderick <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, [log in to unmask]
Date:
Fri, 1 Jul 2005 10:11:57 -0500
Content-Type:
text/plain
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text/plain (60 lines)
We just had such a case with 122 boards. The problem was the damage was
severe enough that the 3.3 volt plane 6 mils down was exposed. This
exposure of the 3.3 volt plane to the ground tie on the pin passed
electrical test but I guarantee that once the board was soldered we would
have a dead short from 3.3 to ground. We rejected the 122 damaged boards.

-Al

-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]] On Behalf Of
[log in to unmask]
Sent: Thursday, June 30, 2005 9:25 AM
To: [log in to unmask]
Subject: [TN] Via holes damaged

Group,

I have a question on via holes damaged by test probes.  We have a
situation where some of the annular ring of the vias used for test
points are being damaged.  I have looked in the IPC-A-610 Rev. D and
also IPC-A-600 Rev. G, but am not finding what I need or am not looking
in the right place.  If anyone knows of the requirements of what is
acceptable or a defect for this type of condition, please let me know.

Thanks.

Mary Jane

Mary Jane Chism
Technical Trainer/ Learning Center
Kimball Electronics Group
email: [log in to unmask] <mailto:[log in to unmask]>
Phone: 812-634-4462
Fax:     812-634-4501


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