Amen to that
Wolfgang
----- Original Message -----
From: "Franklin D Asbell" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, June 14, 2005 6:15 PM
Subject: Re: [TN] PCB rejection criteria
> "Packaging" is not addressed because "packaging" was not the cause, nor
> would they be part of a solution in this specific instance.
>
> Food for thought "why muddle up with pond it only makes finding what you
> are
> looking for that much more difficult"
>
> And might I suggest more leisure time for you...relax...have a cold tasty
> beverage...enjoy the Summer...
>
> Franklin
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of Stadem, Richard
> Sent: Tuesday, June 14, 2005 2:15 PM
> To: [log in to unmask]
> Subject: Re: [TN] PCB rejection criteria
>
> All of these responses address fab pwb cleanliness and overlook a key
> element; packaging.
>
> It has always been a fundamental expectation that pwbs are expected to
> arrive in a clean, dry condition, ready to go directly into production.
> As part of this, packaging of the circuit boards for shipping should
> include a tight hermetic wrap and seal of the pwbs in a "brick" that
> includes a protective paper liner between each pwb within the brick, and
> a dessicant pouch included. Some places have special requirements that
> preclude the paper liner, in order to facilitate the unloading of the
> pwbs from a magazine or mezzanine loader at the beginning of the line.
> But no matter what the packaging requirements are, there should
> certainly not be any scratches that expose copper, nor should there be
> any milling residue, dust, dirt, bug potty or anything else that's not
> on the pwb print.
> The reasons for the hermetic seal is to prevent oxidation of the
> immersion silver, immersion tin, and certain other surface finishes and
> to preserve the dry condition of the pwb.
> If I received pwbs loose inside foam packaging, or simply wrapped but
> not sealed, I would dry the boards by baking per J-STD-033. I really
> have no idea what conditions these boards have been exposed to. For all
> I know, they could have sat inside of a warehouse in the tropics
> somewhere where the RH is >90%.
>
> Its not just for components.
>
> Somewhere in the acceptability requirements listed in IPC 6012B, 9199,
> M105, PAS62250, and QE605A I'm sure there are words addressing these
> fundamental, basic issues.
>
> And I take exception to the statement that "there is no such thing as a
> spotless board". Just what does that mean?
> PWBs should not be "wiped clean". This just deposits lint and dirt into
> the via holes, through holes, and packs dirt and dust into the gaps, say
> between the soldermask and the pads for BGAs.
>
> PWBs should be washed after all processing is done, and be tested on a
> sampling basis for cleanliness.
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of Fineline Circuits,
> Inc
> Sent: Tuesday, June 14, 2005 1:05 PM
> To: [log in to unmask]
> Subject: Re: [TN] PCB rejection criteria
>
> Erick:
> Board fabricators generally touch up any scratched circuits that is
> exposed with mask.
> Also the dust you see may be from routing of the boards and they should
> have been wiped clean before shipping.The vaccuum on the router may not
> be working upto par or the dust collection may be full. There is no such
> thing as a spotless board but they can be clean.You should let your fab
> guys know that this is not acceptable for future orders.
> Hasl with excess solder can be rehot levelled but they have to be in
> panel form.
> I would communicate with the fabricators of all these issues so that
> they can take steps to correct it for future orders.It looks like these
> boards were shipped without inspection.
> Your issues are more procedure related and this does not add to the cost
> of fabrication. These are all standard procedures followed by
> manufacturer.
> Sona Sitapara
> Fineline Circuits Inc.
>
> ----- Original Message -----
> From: "ekalgren" <[log in to unmask]>
> To: <[log in to unmask]>
> Sent: Tuesday, June 14, 2005 11:54 AM
> Subject: [TN] PCB rejection criteria
>
>
>> Good morning everyone,
>>
>>
>>
>> I've got a question on bare PCB's. These are relatively simple boards
>
>> that have been red flagged in incoming inspection for having scratches
>
>> in the soldermask that expose the underlying copper. Now, even I know
>
>> that this is truly a defect. QA has also written up the entire lot of
>
>> boards for being dusty and a couple of the lot for having "excess
>> solder." The excess solder is just a couple of PTH's that are
>> partially filled by the HASL. I'm not sure what the dust is but it
>> blows off easily and doesn't seem to be affecting anything other than
>> the inspector's sense of cleanliness.
>>
>>
>>
>> My question to all of you out there is: how should I handle the dust
>> issue?
>> Is this typical of boards coming in from the shop and should I tell
>> the inspectors to go easier in the future or do I demand spotless,
>> dust free boards from our supplier? I don't want to accept junk but
>> at the same time I don't want to drive costs up by over inspecting.
>> Where does one draw the line?
>>
>>
>>
>> Thanks in advance,
>>
>>
>>
>> Eric Kalgren
>>
>> Manufacturing Engineer
>>
>> Continental Tool and Microwave Company
>>
>> [log in to unmask]
>>
>>
>>
>>
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