I agree with Kerry: we are using even denser boards (>5000 0402 components per boards. We are using either 20x20 or 24x24 pads, with 10 mils space. Almost no tombstone problems. The key is managing the traces attached to the pads: They should be routed from the pad along the component axis for at least 7 mils, then rout them as you wish. 

Ofer Cohen
Quality Manager
Seabridge - a Siemens company

> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of Kerry McMullen
> Sent: Friday, May 06, 2005 19:29
> To: [log in to unmask]
> Subject: Re: [TN] 0402 issues
> 
> Hi Frank,
> I have had a lot of board assemblies with over 1,000 of those 
> little guys per board.  I used the .012 air gap for my 
> footprints with .020 pads with no tombstoning.
> I have found that those 0402's that do tombstone is due to 
> pad to pad imbalance due to the amount of traces going into 
> the pads.  Those you have to deal with the layout and 
> designer to address.
> Hope this helps,
> Kerry
> 
> 
> 
> 
> 
> 
> Frank Kimmey <[log in to unmask]>
> Sent by: TechNet <[log in to unmask]>
> 05/06/2005 01:05 PM
> Please respond to
> TechNet E-Mail Forum <[log in to unmask]>; Please respond to 
> Frank Kimmey <[log in to unmask]>
> 
> 
> To
> [log in to unmask]
> cc
> 
> Subject
> [TN] 0402 issues
> 
> 
> 
> 
> 
> 
> This question is for Assembly Process Engineering types.
> 
> Our designs are suffering from 0402 tombstoning.
> The best feedback I am receiving from our Asian CM is this is 
> caused by footprints.
> As I am a Designer and not a Process Engineer I have been 
> tasked with asking some experts.
> So, here we go:
> 
> We are in the process of redesigning some PCBs that use 0402 
> chip parts (Rs and Cs).
> Our CM is requesting we deviate from our IPC-782 footprints.
> At present IPC782 and 7351 both recommended .016" gap between lands.
> Our CM is requesting reduction to .012"
> 
> Comments?
> 
> 
> Also, we use flooded ground pours due to RF performance and 
> there fore end up with unequal land sizes (one copper defined 
> pad and one soldermask defined pad +.004 in X and Y size) 
> depending on device connections.
> What would be your concerns over this design style?
> Do we need to equalize land sizes at the cost of time in 
> design (literally thousands of parts per board) or can this 
> be relatively compensated for with assembly process (paste, 
> profile, fixturing, etc.)?
> 
> 
> Any help is appreciated
> Thanks,
> FNK
> 
> Frank N Kimmey CID+
> Principal PCB Designer
> Powerwave Technologies Inc
> Office 916-941-3159
> Fax 916-941-3195
> Cellular 916-804-2491
> 
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