Hi Frank! We use a 0.012 inch gap between lands for 0402s and have very few
issues with tombstones. Keep in mind your solderpaste, reflow profile and
whatever else the lands are connected to (external & internal) on the pwb
also play a role in causing tombstone defects. I have seen the unequal land
sizes be a significant tombstone driver. Good Luck.

Dave Hillman
Rockwell Collins
[log in to unmask]




             Frank Kimmey
             <[log in to unmask]
             >                                                          To
             Sent by: TechNet          [log in to unmask]
             <[log in to unmask]>                                          cc

                                                                   Subject
             05/06/2005 12:05          [TN] 0402 issues
             PM


             Please respond to
              TechNet E-Mail
                   Forum
             <[log in to unmask]>
             ; Please respond
                    to
               Frank Kimmey
             <[log in to unmask]
                     >






This question is for Assembly Process Engineering types.

Our designs are suffering from 0402 tombstoning.
The best feedback I am receiving from our Asian CM is this is caused by
footprints.
As I am a Designer and not a Process Engineer I have been tasked with
asking some experts.
So, here we go:

We are in the process of redesigning some PCBs that use 0402 chip parts (Rs
and Cs).
Our CM is requesting we deviate from our IPC-782 footprints.
At present IPC782 and 7351 both recommended .016" gap between lands.
Our CM is requesting reduction to .012"

Comments?


Also, we use flooded ground pours due to RF performance and there fore end
up with unequal land sizes (one copper defined pad and one soldermask
defined pad +.004 in X and Y size) depending on device connections.
What would be your concerns over this design style?
Do we need to equalize land sizes at the cost of time in design (literally
thousands of parts per board) or can this be relatively compensated for
with assembly process (paste, profile, fixturing, etc.)?


Any help is appreciated
Thanks,
FNK

Frank N Kimmey CID+
Principal PCB Designer
Powerwave Technologies Inc
Office 916-941-3159
Fax 916-941-3195
Cellular 916-804-2491

---------------------------------------------------
Technet Mail List provided as a service by IPC using LISTSERV 1.8e
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt or (re-start) delivery of Technet send e-mail to
[log in to unmask]: SET Technet NOMAIL or (MAIL)
To receive ONE mailing per day of all the posts: send e-mail to
[log in to unmask]: SET Technet Digest
Search the archives of previous posts at: http://listserv.ipc.org/archives
Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16
for additional information, or contact Keach Sasamori at [log in to unmask] or
847-615-7100 ext.2815
-----------------------------------------------------

---------------------------------------------------
Technet Mail List provided as a service by IPC using LISTSERV 1.8e
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL)
To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest
Search the archives of previous posts at: http://listserv.ipc.org/archives
Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815
-----------------------------------------------------