Karl,
For clarification purposes, What is Sun's definition of high reliability
boards? Class 2 or Class 3.
Regards,
Randy Reed
Merix Corporation
-----Original Message-----
From: IPC-600-6012 [mailto:[log in to unmask]] On Behalf Of Karl Sauter
Sent: Thursday, April 21, 2005 9:27 AM
To: [log in to unmask]
Subject: Re: [IPC-600-6012] Proposed IPC-6012B Change for SnPb in SMOBC
I agree with Chris Conklin's minor change; adding "Solder may extend
0.010 inches on the circuitry underneath the soldermask at the
interfaces of the soldered areas and non-soldered areas."
We are very concerned with the potential for solder wicking down
adjacent escape vias, particularly at passive and BGA sites where
soldermask coverage is minimal due to short connecting trace lengths.
We require these sites to be reworkable at least twice. These areas at
the bare board level should be closely examined at the earliest opportunity.
Therefore we would like to see a tighter requirement for high
reliability printed wiring boards, allowing the solder to extend at most
0.005 inches on the circuitry underneath the soldermask at the
interfaces of the soldered areas and non-soldered areas.
Regards,
Karl Sauter
Sun Microsystems
> From: IPC-600-6012 [mailto:[log in to unmask]] On Behalf Of Conklin, C J
> Sent: Wednesday, April 20, 2005 4:02 AM
> To: [log in to unmask]
> Subject: Re: [IPC-600-6012] Proposed IPC-6012B Change for SnPb in SMOBC
>
> I would agree with the wording as proposed by Clarence Knapp with one
minor
> change just for consistency:
>
> "Solder may extends 0.010" on the circuitry underneath the solder mask
> at the interfaces of the soldered areas and non-soldered areas.
> Final finish used to preserve solderability under SMOBC on areas not to be
> soldered is permitted on 1% of the conductor surfaces for Class 3 and 5%
> of the conductor surfaces for Class 1 and 2."
>
> Interestingly, I just had this same conversation with Mark Buechner on
> Friday. We build very few solder plated and selectively striped PWBs.
> However, we do produce a significant number of conventional SMOBC PWBs
with
> HASL. From time to time, we end up with small areas where the circuit has
> solder mask over solder. Criteria that would allow this to be accepted on
a
> limited basis would have our approval. Therefore, we would vote yes for
> criteria that covered both the encroachment under the mask at the
interface
> for selectively stripped parts and solder, or whatever final finish is
being
> used, under solder mask on interior circuits as described by Mike Hill.
>
> Best regards,
>
> Chris Conklin
> PWB Quality Engineering
> Lockheed Martin Systems Integration - Owego
> 1801 State Route 17C MD0409
> Owego, NY 13827
> Phone: 607-751-4251 FAX: 607-751-7714
> e-mail: [log in to unmask] <mailto:[log in to unmask]>
> -----Original Message-----
> From: John Perry [mailto:[log in to unmask]]
> Sent: Tuesday, April 19, 2005 9:05 AM
> To: [log in to unmask]
> Subject: [IPC-600-6012] Proposed IPC-6012B Change for SnPb in SMOBC
>
> Colleagues,
>
> The IPC D-33a Rigid Board Performance Task Group is beginning the
> development of an Amendment 1 to IPC-6012 Revision B. Relative to this
> is a request to modify and append text in section 3.5.4.7, Final Finish
> Coverage (Areas not to be soldered).
>
> Background on change request:
>
> A printed board was found to have small amounts of Tin Lead under the
> solder mask with reflow/SMOBC finish. The part has been fabricated
> using the selective solder strip process. The customer rejected the
> parts for small amounts of tin lead found on bare copper and under the
> solder mask, claiming with Tin Lead, the part no longer was Solder Mask
> over Bare Copper. There is currently no IPC specification that
> prohibits such Tin Lead on the bare copper. However, at some point it
> becomes a workmanship issue per IPC 6012B paragraph 3.3.9.
>
> Rationale for change request:
>
> This new accept/reject criteria provides a check and balance for the tin
> lead strip process (i.e., the process is not capable of absolute ZERO
> tin lead as there is always trace amounts on some circuits) and at the
> same time we don't want to be throwing away printed boards that are
> functionally fine.
>
> Proposed Change within 3.5.4.7 of IPC-6012B:
>
> 3.5.4.7 Final Finish Coverage
> Final finish shall meet the solderability requirements of J-STD-003.
>
> 3.5.4.7.1 Exposed Copper (Areas not to be soldered) Exposed copper on
> areas not to be soldered is permitted on 1% of the conductor surfaces
> for Class 3 and 5% of the conductor surfaces for Class 1 and Class 2.
> Coverage does not apply to vertical conductor edges.
>
> 3.5.4.7.2 Tin-Lead under SMOBC
> Tin or Tin Lead under SMOBC on areas not to be soldered is permitted on
> 1% of the conductor surfaces for Class 3 and 5% of the conductor
> surfaces for Class 1 and 2.
>
> If you approve the proposed change without comment, please send your
> approval, by May 3rd, to [log in to unmask] If there is a need to comment
> on and discuss this within the task group, please respond through this
> e-mail forum.
>
> Thanks,
>
> John Perry
> Technical Project Manager
> IPC
> 3000 Lakeside Drive # 309S
> Bannockburn, IL 60015
> [log in to unmask]
> 1-847-597-2818 (Phone)
> 1-847-615-7105 (Fax)
> 1-847-615-7100 (Main)
>
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