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March 2005

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Stephansson Sean-ESS060 <[log in to unmask]>
Date:
Thu, 10 Mar 2005 12:20:20 -0500
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Kerry,

Could you please cite the studies that you reference?


Best regards,

Sean Stephansson
Process Engineer
Rapid Product Realization Center
Motorola
(954)723-3557
[log in to unmask]


-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Kerry Bode
Sent: Wednesday, March 09, 2005 1:04 PM
To: [log in to unmask]
Subject: Re: [TN] Microvias & plating


Hello,

The micro-via with dimples is fairly common and is deployed in many high reliability products today. The micro-via should be of a size that does not create a void or out gassing condition during assembly. I have seen studies that if the via dimple is greater than .006 in diameter it becomes a concern during assembly. Solder paste typically will fill in the dimple. Japan PWB fabricators have developed a method to plate the vias closed, however it's costly.

-----Original Message-----
From: Michaloski, Denise [mailto:[log in to unmask]]
Sent: Wednesday, March 09, 2005 11:22 AM
To: [log in to unmask]
Subject: [TN] Microvias & plating

Does anyone call out the microvias to be plated flush? (This particular board is immersion gold) Our in house assembly is asking for this because they do not like the dimples left on SMT pads from the microvias (especially on BGA pads). Anyone who uses microvias, please let me know how you deal with your microvias. TIA Denise Michaloski, C.I.D. Windermere ITS 443-716-2510 [log in to unmask]


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