This table is problematic, to my mind, from a number of vantage points.
But to try to address your question: I have also looked into this chart
and tried to work to it (with it?) and wondered where the values came
from, what testing they were based on ... the best answer I could get was
that old Navy powersupply guidelines and old conductor current carrying
rating charts that were developed on 2 layer boards were "extended" to
multilayers with some "expert estimations" used for the guidance values.

I found the Navy powersupply design document ... it wasn't that helpful;
but it did suggest huge separations between *planes* for safety based on
voltage bias. Using those guidelines we could never build 24 layer .093"
multilayers ... anyway

I also talked with a lot of laminate manufacturers and a lot of
fabricators about this topic... seems there is a rule of thumb that the
FR4 dielectric withstand voltage value needs to be derated for real
boards. The DWV test is a full plane over plane test, while we have all
these features etched onto our planes which make for little accumulators
of localized energy concentrations; plus we drill holes in these things
and the holes can crack or craze the glass bundles and sometimes debond
the resin from the glass; there are all sorts of things that happen when
we make real boards that aren't adequately accounted for when the laminate
is tested in a "virgin" state.

The table makes no differentiation between in-plane and inter-plane
separations; but it does make a significant difference between internal
feature separation and external feature separation. The failure modes
inside a board can be quite different from those on that act on external
features.

Based entirely on anecdotal and experiential information, I treat the
values as minimums and try to add margin. While it might seem that the
table is conservative relative to the DWV values you get from laminate
spec sheets, it really isn't.

And you're right; I wish there were an algorithm so we could punch in each
board's unique features and get the minimum spacing as a function of bias,
but it isn't built on an algorithm. You can tell that the values are a
step function: a doubling at some arbitrary point based on voltage. So, if
I have 99 volts I can have half the separation of what I would need for
100 volts? I don't think so. That's why I round-up to the next "step" on
the chart when the voltage gets close to the step function.

Anyway... a bit of a ramble, but unfortunately that is how it is. Maybe
some day some one will have the time to run a decent experiment to nail
this down, but until that time this guidance is the best that we have.
Maybe someone can add something to this ...

Valerie

----- Message from - Bogert <[log in to unmask]> on Wed, 2 Feb 2005 18:55:57
-0500 -----

      Subject: Technical basis for Table 6-1 of IPC-2221


February 2, 2005

Table 6-1 defines minimum electrical spacing requirements between traces
on
a PWB.  What is the technical basis for the Table?  Is there a formula
associated with the values in the table?  For example, if I have a PWB
operating at 30 volts DC, the minimum spacing required between internal
traces is 0.05 mm.  What if a PWB operates at 30 VDC but only has 0.04 mm
spacing, is there a technical concern?  Based on what formula or technical
consideration?

The minimum spacing in the Table are much less than the electric strength
requirements for FR4.  For example, my understanding is that FR4 is about
1250 volts/mil.  Therefore, at 1 mil of spacing the PWB should be able to
withstand 1250 volts between conductors.

The values in the table are also different than those included in UL 840.
Why?


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Any help you can offer on this point would be appreciated.