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February 2005

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Subject:
From:
JaMi Smith <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, JaMi Smith <[log in to unmask]>
Date:
Fri, 25 Feb 2005 13:02:45 -0800
Content-Type:
text/plain
Parts/Attachments:
text/plain (326 lines)
Steve,

The more I think about it the more I realize that they are in fact woried about what
will vary where, in terms of impedance.

For some reason I have a hunch that they may have a BGA with LVDS routed as 50 ohm
differential pair controlled impedance structures, which would probably be the most
sensitive to variations in the dialectric thickness. If this is so, then you need to
identify their location and use cores where you can there so as to limit the
variation. If their are no differential pair structures anywhere, then you have a
little more latitude, but you (your customer) still should probably choose the core
locations in your stackup carefully. This of course presupposes that you are going
to use cores in the stackup.

Oddly enough, I usually find that when I try and control my critical impedances with
by placing cores in certain locations, the board house usually comes back to me
asking if they can build it differently, because it usually is a slightly more
complex stackup than the simple "start in the middle and add prepreg and foil"
approach, which seems to be so prevalent today.

I notice a parrallel response where someone suggests recalculating things for an
easier and more standard impedance approach, and I would agree, but I would first
find out what your customers real hidden needs and concerns are, and see how they
need to be accomodated first, before you start trying to second guess the design. By
that I mean it looks as if things do in fact need to be standardized a bit, but your
customer may in fact be trying to do something here that he is not too sure of
himself, and I would say that your best bet is to talk to him first.

JaMi


----- Original Message -----
From: "Stephen Gregory" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, February 25, 2005 11:58 AM
Subject: Re: [TN] Manufacturability of PCB Stack-up...


> Hi JaMi!
>
> Theirs...
>
> -Steve-
>
>
>
> |---------+---------------------------->
> |         |           JaMi Smith       |
> |         |           <jamismith@SBCGLO|
> |         |           BAL.NET>         |
> |         |           Sent by: TechNet |
> |         |           <[log in to unmask]>|
> |         |                            |
> |         |                            |
> |         |           02/25/2005 01:56 |
> |         |           PM               |
> |         |           Please respond to|
> |         |           TechNet E-Mail   |
> |         |           Forum; Please    |
> |         |           respond to JaMi  |
> |         |           Smith            |
> |         |                            |
> |---------+---------------------------->
>
>-----------------------------------------------------------------------------------
---------------------------|
>   |
|
>   |       To:       [log in to unmask]
|
>   |       cc:
|
>   |       Subject:  Re: [TN] Manufacturability of PCB Stack-up...
|
>
>-----------------------------------------------------------------------------------
---------------------------|
>
>
>
>
> Steve,
>
> Your customer probably has some concerns with variation in the specific
> impedances,
> which is why he is asking about the "varying dielectric thicknesses".
>
> Why are you showing so many individual "dielectric" segments in your
> diagram?
>
> Surely they can't all be made of prepreg with no cores anywhere.
>
> Maybe that is what he is questioning.
>
> When I am trying to hold some portion of the stackup to certain dimensions,
> I
> usually specify that by specifying certain cores in certain locations,
> which at
> least eliminates some of the variables, and lets me chose where the
> remaining
> variables are.
>
> If you truly are building the entire thing with prepreg, then individual
> thicknesses
> in the final outcome are strictly a function of the laminating press.
>
> Who's stack up diagram and calculations, yours or theirs?
>
> JaMi
>
>
>
> ----- Original Message -----
> From: "Stephen Gregory" <[log in to unmask]>
> To: <[log in to unmask]>
> Sent: Friday, February 25, 2005 11:18 AM
> Subject: Re: [TN] Manufacturability of PCB Stack-up...
>
>
> > Actually, I don't know enough about the actual fabrication process to
> have
> > any...it was our customer who had the question.
> >
> > I guess they were worried (as I said in my earlier post) about the
> varying
> > dielectric thicknesses posing some sort of difficulty...you just use
> > different
> > prepreg thicknesses to laminate it all up, right?
> >
> > Copper all seems pretty balanced to me, so no warping issues should
> > occur...
> >
> > Me not being a true-blue board guy, I thought this would be a good
> Technet
> > question...
> >
> > Kind regards,
> >
> > -Steve Gregory-
> > Senior Process Engineer
> > LaBarge Incorporated
> > Tulsa, Oklahoma
> > (918) 459-2285
> > (918) 459-2350 FAX
> >
> >
> > |---------+----------------------------->
> > |         |           "Franklin D       |
> > |         |           Asbell"           |
> > |         |           <fasbell@networkci|
> > |         |           rcuits.com>       |
> > |         |                             |
> > |         |           02/25/2005 01:05  |
> > |         |           PM                |
> > |         |                             |
> > |---------+----------------------------->
> >
> >
> ----------------------------------------------------------------------------------
-
>
> ---------------------------|
> >   |
> |
> >   |       To:       "'TechNet E-Mail Forum'" <[log in to unmask]>,
> <[log in to unmask]>                    |
> >   |       cc:
> |
> >   |       Subject:  RE: [TN] Manufacturability of PCB Stack-up...
> |
> >
> >
> ----------------------------------------------------------------------------------
-
>
> ---------------------------|
> >
> >
> >
> >
> > Steve,
> >
> > That doesn't look difficult at all...what are your concerns???
> >
> > Franklin D Asbell
> > Network Circuits, Inc.
> > Irving, Texas 75061
> > 972-313-1400
> >
> >
> >
> > -----Original Message-----
> > From: TechNet [mailto:[log in to unmask]] On Behalf Of Stephen Gregory
> > Sent: Friday, February 25, 2005 12:54 PM
> > To: [log in to unmask]
> > Subject: [TN] Manufacturability of PCB Stack-up...
> >
> > Happy Friday All!
> >
> > I've posted a drawing of a PCB layer stack-up at:
> >
> > http://www.stevezeva.homestead.com/files/Stackup.jpg
> >
> > I'd like to verify its manufacturability.  The reason for the
> verification
> > is that there
> > are dielectric thicknesses that vary quite a bit from layer to layer.
> >
> > Can anybody comment on this?
> >
> > Kind regards,
> >
> > -Steve Gregory-
> > Senior Process Engineer
> > LaBarge Incorporated
> > Tulsa, Oklahoma
> > (918) 459-2285
> > (918) 459-2350 FAX
> > __________________________________________________________________
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> to
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> and
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> >
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>
>
>
> __________________________________________________________________
> This message may contain information that is privileged and confidential to
> LaBarge, Inc.  It is for use only by the individual or entity named above.
> If you are not the intended recipient, you may not copy, use or deliver
> this message to anyone.  In such event, you should destroy the message and
> kindly notify the sender by reply e-mail.
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ext.2815
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