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February 2005

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Subject:
From:
Richard Kraszewski <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Richard Kraszewski <[log in to unmask]>
Date:
Tue, 1 Feb 2005 16:18:36 -0500
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What type of failure mechanism(s) would you expect?

Rich Kraszewski 
Advanced Manufacturing Engineer - KEDS
Phone:  260.925.8919
 
 
 


-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Jeffrey Bush
Sent: Tuesday, February 01, 2005 3:40 PM
To: [log in to unmask]
Subject: Re: [TN] Behavior of Via's in low temperature cycling


Thin copper plating, poor ductility of plating deposit, under cured
resin system - to name a few.

Jeffrey Bush
Director, Quality Assurance and Technical Support

VERMONT CIRCUITS INCORPORATED
  76 Technology Drive - POB 1890
    Brattleboro, Vermont 05302
      Voice: 802.257.4571.21 Fax: 802.257.0011
           http://www.vtcircuits.com
 

-----Original Message-----
From: Richard Kraszewski [mailto:[log in to unmask]] 
Sent: Tuesday, February 01, 2005 3:05 PM
To: [log in to unmask]
Subject: [TN] Behavior of Via's in low temperature cycling

I have a 6 layer board with a 10-mil standard through hole (not micro)
via. 
 
Trying to understand what type of stresses 7 factors  would drive
failure of this via at cycling from -40degC to 125degC with normal FR4. 
 
Any thoughts or sources of references would be appreciated. 
 
Thanks.

Rich K / KEDS 

 

 

 

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