Rich,
You should expect mechanical failure modes. Things like cracked vias
are a possibility. I've seen via test points popped of the board. Best way
to characterize specific failures would be to run a board test after or
during exposure to stress, then root causing per failure data....again
thoroughly inspect, under microscope, for physical mechanical damage.
Barrie Fraley
EMC Corporation
Electrical DVT/HALT
508-249-4472
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Richard Kraszewski
Sent: Tuesday, February 01, 2005 4:19 PM
To: [log in to unmask]
Subject: Re: [TN] Behavior of Via's in low temperature cycling
What type of failure mechanism(s) would you expect?
Rich Kraszewski
Advanced Manufacturing Engineer - KEDS
Phone: 260.925.8919
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Jeffrey Bush
Sent: Tuesday, February 01, 2005 3:40 PM
To: [log in to unmask]
Subject: Re: [TN] Behavior of Via's in low temperature cycling
Thin copper plating, poor ductility of plating deposit, under cured
resin system - to name a few.
Jeffrey Bush
Director, Quality Assurance and Technical Support
VERMONT CIRCUITS INCORPORATED
76 Technology Drive - POB 1890
Brattleboro, Vermont 05302
Voice: 802.257.4571.21 Fax: 802.257.0011
http://www.vtcircuits.com
-----Original Message-----
From: Richard Kraszewski [mailto:[log in to unmask]]
Sent: Tuesday, February 01, 2005 3:05 PM
To: [log in to unmask]
Subject: [TN] Behavior of Via's in low temperature cycling
I have a 6 layer board with a 10-mil standard through hole (not micro)
via.
Trying to understand what type of stresses 7 factors would drive
failure of this via at cycling from -40degC to 125degC with normal FR4.
Any thoughts or sources of references would be appreciated.
Thanks.
Rich K / KEDS
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