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January 2005

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Subject:
From:
"Brooks,Bill" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Brooks,Bill
Date:
Tue, 11 Jan 2005 12:37:38 -0800
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Paul,

To answer your question, as long as you have specified the tolerance you
have an "accept/reject" criteria... weather through the notes on your
drawing or through the IPC Specification that is referenced. It's up to you
to determine if the tolerance is acceptable or not.  I have seen wide
variations in tolerance schemes for specifying line widths and land areas on
boards. Percentage deviation from nominal is common... some put a plus/minus
range on specific features like lines under a given size...

  Care should be taken in trying to drive the design by the tightening
tolerances. A designer does not "improve a design" by 'tightening
tolerances'. You only end up running the cost of the board up and the yields
down. The tolerances defined let the manufacturer know 'what range of
variances from nominal are acceptable' and that you will reject any that
fall out of that tolerance because they will not work in the design.

A designer should know what will fit or work in the design and what will
not. Tolerances are useless if the designer has not reviewed them for 'fit
form and function' and set them to allow the MAXIMUM variances in the
design... thus realizing the maximum cost savings, yields and
reproducibility.

If the design will tolerate feature variances from the 'ideal' or nominal as
designed, these variances need to be communicated to the vendor by correctly
defining the tolerances for the features of the board. This also means
knowing the capabilities of the vendor you choose to do the manufacturing.
Some vendors do not possess the machines and processes to support tighter
tolerances... Obviously, you would have to send boards to them that can
still work with less restrictions on things like over and under etch,
plating thickness, drill accuracy and run out of their machines, etc... The
tighter the tolerance... the more difficult to manufacture... thus the more
expensive to manufacture and better machinery required. Save your more
difficult designs for more the capable vendors but set your tolerances to
the level that is 'just' acceptable.

Best regards,


Bill Brooks - KG6VVP
PCB Design Engineer , C.I.D.+, C.I.I.
Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510
e-mail:[log in to unmask]
http://www.dtwc.com
http://pcbwizards.com

Quote "Anyone can design a strong bridge, but it takes an engineer to design
one that will 'just' not fall down..." - Anonymous

-----Original Message-----
From: O'Connor Paul [mailto:[log in to unmask]]
Sent: Tuesday, January 11, 2005 7:05 AM
To: [log in to unmask]
Subject: [TN] Surface Mount Land 'over' Etching

Hello,

I have a question that someone may have had some experience with, my PCB's
are fabricated to IPC 6011 / 6012 class 2 as per IPC-A-600.
Question is on the minimum conductor width, the standards define & measure
the minimum width of the conductor at its base (IPC-A-600 Section 3.2), but
in the case of a fine pitch surface mount pad (I'm assuming conductor as
defined in IPC6012 Section 3.5.1 - relates to both traces & surface mount
lands) its possible to have the measurement at the base of the device within
spec yet the etching process can reduce the width at the surface of the land
by so much that there are serious assembly difficulties, I've seen
variations of between 10 & 50% reduction on the surface of the lands between
different batches. I'm aware that this is usually only an issue when there
is a combination of fine pitch & heavy copper, my proposed solution it to
tighten the spec to specifically state that the point of narrowest conductor
width can not reduce below in my case 25%,  I'm wondering has anybody else
had a similar experience & if so what was the approach to resolving it ?

Thank You.

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