Paul
You are bringing up a fairly common issue. Actually you are bringing up a
couple of fairly common issues.
First let me make a correction to something you said then comment on your
SMT feature size problem
IPC specs DO NOT state OL conductor width is to be measured at the bottom of
the trace. The spec says the conductor width is defined by the outer most
edge of the conductor. Granted in most cases, this is the bottom of the
feature since that part etches last. But there are exceptions.
Specifically any boards that retain the etch mask (e.g. full body
electrolytic nickel/gold), the widest part of the trace is likely going to
be the top of the conductor.
With that clarification in mind (this will come up again later), I'm not
advocate of tightening your spec. I think the underlying issue is you are
not accurately specifying your requirement. Tightening the tolerance when
you are not asking for the correct thing might get you want, but it will
also likely end up with higher costs since you can expect a decrease in
yields. Or the supplier will react to the tightened specification by
adjusting something else that you don't want.
I've run into this issue many times before. I'll illustrate with an
example. I had a customer specify a finished hole with a tolerance of
+.006/-.000". We built the boards to the appropriate tolerance but a
competitor used the more common, but incorrect +/-0.003" tolerance. As a
result holes on the competitor's boards were undersized. To "fix" this
issue, the customer tightened the spec to +0.004"/0.000". This forced me to
reduce my drill size, increasing the likelihood of having undersized holes.
Tightening the spec led to exactly the opposite of the intended solution.
But I digress.
My recommendation is specify that you want the tops of the SMT features on
the boards to be a certain width. The board fabricator should then be able
to selectively compensate these pads to meet your requirements. We see this
quite often and have processes setup to make the necessary modifications.
No tighter spec required. Of course this is not without potential issues.
Since the SMT features will have to be made wider to meet your spec, you
need to increase the minimum designed space you use around these features or
you will create a new problem.
There's an alternative way to do this which is to oversize your SMT pads
during design so the tops come out at the correct width when the bottoms are
in spec. While this seems easy at first, it is fairly complicated. The
amount of compensation depends on many factors including copper foil weight,
the relative amounts of electroless, strike and pattern plate, the
photoresist used, the minimum spacing, and the surface finish specified
(told you that would come back again). You would have to take all o this
into account when designing your board. Plus, there's no guarantee that two
fabricators will process the board exactly the same so what works for Fab A
is not correct for Fab B.
For this reason, the best solution is to specify exactly what you want and
allow the fabricator to take it from there.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of O'Connor Paul
Sent: Tuesday, January 11, 2005 7:05 AM
To: [log in to unmask]
Subject: [TN] Surface Mount Land 'over' Etching
Hello,
I have a question that someone may have had some experience with, my PCB's
are fabricated to IPC 6011 / 6012 class 2 as per IPC-A-600.
Question is on the minimum conductor width, the standards define & measure
the minimum width of the conductor at its base (IPC-A-600 Section 3.2), but
in the case of a fine pitch surface mount pad (I'm assuming conductor as
defined in IPC6012 Section 3.5.1 - relates to both traces & surface mount
lands) its possible to have the measurement at the base of the device within
spec yet the etching process can reduce the width at the surface of the land
by so much that there are serious assembly difficulties, I've seen
variations of between 10 & 50% reduction on the surface of the lands between
different batches. I'm aware that this is usually only an issue when there
is a combination of fine pitch & heavy copper, my proposed solution it to
tighten the spec to specifically state that the point of narrowest conductor
width can not reduce below in my case 25%, I'm wondering has anybody else
had a similar experience & if so what was the approach to resolving it ?
Thank You.
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