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December 2004

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From:
paul reid <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, paul reid <[log in to unmask]>
Date:
Mon, 6 Dec 2004 14:54:48 -0500
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Hi Swati,

I have been following this thread and I understand that this phenomenon is
not particularly linked to a heating excursion.  I believe that what you are
seeing is separation between the hole wall and the copper plating in the
barrel of the hole on an unstressed PTH.  I believe that this condition is
covered in IPC 6012.

As for causes for this condition, it may happen without thermal stress, when
the electroless copper in the PTH is not adhering to the dielectric.  One
test you could do is to look through a back lit PTH, looking down from the
surface of the board into the barrel, using a 100X stereoscope, the barrel
of the hole may not look round.  If the hole appears asymmetrical, expect
hole wall pull away.

Assuming you have not experienced interconnect separation, then the foil to
copper interface, at the internal layers, may be all that is holding the
barrel in place.  I would compare it to spot welds in a copper barrel.  Spot
welds at each interconnection, with a separation of the copper barrel from
the hole wall, in between these attachment points.

If gross hole wall pull away is the condition you are observing, you would
expect that the stresses from the thermal excursions of assembly would
degrade the interconnection quickly.  To confirm or refute that assumption
there are two tests you may try.  You could try "Thermal Stress, Plated
Through-holes" IPC TM 650, number 2.6.6 and pay particular attention to the
quality of interconnections during your microscopic examination.  The
problem is that the test is limited in the number of holes you will be able
to observe microscopically and of course there is a degree of luck required
to randomly hit a bad hole.

If you happen to have IST coupons with your boards you could use  "DC
Current Induced Thermal Cycling" IPC TM 650, number 2.6.26.  I would expect
cycles to failure to be reduced by around 50%.  Because IST testing stops at
a 10% increase in resistance, you could pass current through the failing
circuit and use a thermal camera to find the hole with the highest
resistance (hottest hole).  Then cross section the worst one out of hundreds
of holes and determine the failure mode.  Particular attention should be
paid to the interconnection quality because stress will be focused to
interconnections.

If you elect to use boards with this condition, pre-baking before assembly
would be very wise.


Paul Reid

PWB Interconnect Solutions
613-596-4244 Ext. 229

-----Original Message-----
From: Parial Swati [mailto:[log in to unmask]]
Sent: Sunday, December 05, 2004 11:35 PM
To: [log in to unmask]
Subject: Re: [TN] Clarification about Hole wall separation


Dear Werner,
Thanks a lot for your feedback.
Actually we are observing this particular  phenomena in the boards before
assembly.
What I mean to say is that we are observing this problem in the
microsection that we do in our lab.
We observe this in boards with HASL finish as well as ENIG finish.
Could you throw more light about this phenomena ?

Thanks and warm regards,
Swati...


|---------+---------------------------->
|         |           Werner Engelmaier|
|         |           <[log in to unmask]
|         |           OM>              |
|         |           Sent by: TechNet |
|         |           <[log in to unmask]>|
|         |                            |
|         |                            |
|         |           12/04/2004 09:06 |
|         |           PM               |
|         |           Please respond to|
|         |           TechNet E-Mail   |
|         |           Forum; Please    |
|         |           respond to       |
|         |           Engelmaier       |
|         |                            |
|---------+---------------------------->

>---------------------------------------------------------------------------
-----------------------------------|
  |
|
  |       To:       [log in to unmask]
|
  |       cc:       (bcc: Parial Swati/NAN/ATS/IN)
|
  |       Subject:  Re: [TN] Clarification about Hole wall separation
|

>---------------------------------------------------------------------------
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Hi Swati,
Hole wall separation and resin recession occur during cooling from
soldering
process temperatures. During reflow soldering of the assembly, one of the
hottest part of the assembly is the PCB. The PCB resin is significantly
above its
glass transition temperature, and has a very high CTE. This expansion is
constrained/resisted by the PTV copper barrel. If the barrel plating is
thin and/or
the attached inner-layer pads are spaced too far apart [particularly at
prepreg layers], the barrel walls will deform inwards. Some of this
deformation is
elastic, but can be plastic as well. This plastic deformation of the barrel

wall prevents the copper barrel to resume its original geometry on cooling
when
the resin shrinks back to its original volume. Thus, the copper stays where
it
is, the resin returns to its original geometry--violá, "hole wall
separation
and resin recession."
You can prevent hole wall separation and resin recession by reducing the
soldering temperatures (not a good idea if you want to have good solder
joints--and it will be getting worse with this lead-free insanity), plate
thicker copper
barrel walls, use non-functional inner-layer pads, avoid thick prepreg
layers, have a low resin content in your lay-up.

Regards,
Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL 32174 USA
Phone: 386-437-8747, Fax: 386-437-8737, Cell: 386-316-5904
E-mail: [log in to unmask], Website: www.engelmaier.com


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