Gary,
There are a few things that you may want to be clarified here before you go any
farther, and which you may want to consider among the various answers that you will
get to these questions.
1.) If you are using vias that are "plugged", irrespective of the plugging
technology, and the irrespective of the type of via (Thru Hole, Blind, Micro Via,
etc.), there should be no problem at all with putting an 0402 or 0603 capacitor on
the back side of the board, where you use "via in pad" technology, providing that
the pad pattern is compatible with the spacing of the vias. This should be no
different than any other board with components on the bottom side of the board, and
the only real problem that you may encounter might be standard "thermal isolation"
issues, just as you would in any other circumstance where you want to "decouple" a
power or ground plane, and solder a component to a pad hooked directly to that
plane. You may or may not want to additionally consider using a "glue mask" just as
you would in any other situation where you have components on the bottom side of the
board.
2.) DRC, in any system (you did not state what board design system you are using),
is nothing more than a "Design Rule Check" against a standard set of assumed design
parameters, which work in general for most situations. Some systems even allow you
the ability to juggle those parameters to be able to allow for certain
circumstances. There are times however, when you must "think outside of the box",
and intentionally ignore what your DRC is telling you. The current situation will
probably generate a "DRC Error" no matter what type or brand of board design
software you are using, but that doesn't mean that you can't just ignore it, since
you have a valid reason to do so, and proceed on your own and cut the board anyway.
This is not to say that "Design Rules" are made to be broken, but rather that the
implementation of the "Design Rules" by the programmers of whatever software you are
using simply didn't envision the exception that you have come up with. I would
however place a note somewhere in the design file that documents the exception, so
that the next person who works on the design doesn't curse you and call you an idiot
because he doesn't understand what you did and why. Never think that you can't do
something just because something generated a "DRC Error". To begin with there isn't
a system out there that doesn't make an "Error" of it's own somewhere in generating
"DRC Errors" (i.e. there is no perfect system that is right all of the time anyway),
and once again, if you have a valid reason to do it, ignore the "DRC Error" and go
ahead and do what you need to do to produce the board.
Respecting the issue of "thermal isolation" mentioned above, I will add an
additional two cents worth here, even though it is unsolicited.
While most people don't really think about it to much, "thermal isolation", in most
cases is equivalent to "electrical isolation", and the case in point is no
exception.
For the most part, I generally advocate using "Direct Connect" of vias to the power
and ground planes under a BGA, simply to eliminate the "Swiss Cheese Effect" of most
"Thermal Relief" patterns, which usually decimate anything that there may have been
to begin with in terms of a plane, and look instead to getting the necessary
"thermal
isolation" required to properly solder the BGA ball to the pad by using a small
"dogbone" connecting trace between the pad and the via itself. Usually this
"dogbone" trace is quite short, and as a consequence, it can offer good thermal
isolation while at the same time being a good low inductance power connection,
somewhat equivalent to what we would use to isolate a normal SMT pad from a ground
plane on the outer surface of the board in any other circumstance. In other words,
just use the standard thickness for your power and ground "dogbone traces" that you
use every place else, and don't "beef it up" like most people do. I usually use an 8
mil trace here for all connections, and it usually provides enough "thermal
isolation" from the planes for proper soldering, while at the same time providing
enough copper for an individual low inductance power or ground connection.
The problem here however is that on the bottom side of the board we want to use a
via in pad situation, which virtually dictates that the via be isolated from the
plane by a "Thermal Relief" if we ever want to be able to solder the capacitor in
place, which means that in at least some instances, where we are going to have a
component pad on the bottom side of the board, we also need a "Thermal Relief" in
the corresponding planes.
This brings up a problem that many of the board design systems out there are not
equipped to deal with, and that is how to have a mixture of "Thermal Reliefs" and
"Direct Connects", in the same localized area, and even involving the same nets in
many cases. While most systems may allow you to establish different "connect styles"
for different classes of nets, or in different locations, many fall short of
allowing you to do that on a pin by pin, or via by via, basis.
My solution to this problem is to define all connections as "Direct Connections",
and then go in there via at a time when necessary, and build a "Thermal Relief" out
of the appropriate sized arc segments, and then copy them onto the appropriate plane
where ever I specifically need the "Thermal Relief", such that I make my own, where
ever I want them. I use a variation of this trick when I need to isolate a via from
a plane, such as in the case where I might tie a control line input to a BGA either
high or low to perform a certain function, but which I may want to change later, and
in this case, I just put a complete little "donut" on the corresponding plane layer,
around that particular via, so that it cannot directly connect internally to the
plane, under the BGA where I cannot get at it, which allows me to route the
connection to make the appropriate connection on the back side of the board, where
it can be cut free and rewired if necessary.
I know that's a lot for two cents, but for whatever it's worth . . .
JaMi Smith
* * * * * *
----- Original Message -----
From: "Gary Boccoleri" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, December 08, 2004 5:04 PM
Subject: [DC] FW: Bypass caps under BGAs using via in pad
pad
Hi All,
I'm looking at a spec for a new processor we may be using. They
recommend using via in pad and show a diagram of how to place 0402
bypass caps right on the vias under the chip. Has anybody done this?
This brings up a few questions. Since 2 adjacent vias will form the
footprint for the caps, should I make the bottom pad of the via a square
that approximates the pads I normally use on these caps? How do I place
the caps without creating DRCs? Will our assembly house be completely
dumbfounded when they see this? Is this whole idea just a figment of
some engineers imagination with no basis in reality?
Thanks for all help
Gary Boccoleri
Bivio Networks
925-924-8621
www.bivio.net
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