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November 2004

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Subject:
From:
"Macko, Joe @ IEC" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Macko, Joe @ IEC
Date:
Tue, 30 Nov 2004 13:31:00 -0800
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Fellow Technets,

Two smt type components we want to install on a gold plated pwb have from
0.5 to 1.0  um gold plating over 2 - 6 um of nickel.  J-STD-001C, paragraph
5.4.1, Gold Removal states that "Gold shall be removed from 95% of all
surfaces of surface mount components to be soldered regardless of gold
thickness".   The board is being assembled to class 3 requirements.  These
smt components are leadless type components with castellated terminations
provided on tape and reel and would not be easy to tin with solder .....

Would someone please help clarify this requirement.
Also, what is the latest IPC document that calls out the level of gold
required before "embrittlement" is a concern.  Over the years, I have heard
and read numbers like 0.3 to 3% by wt. and from 5 to 100 u-inches. (Not sure
how to covert a (% by wt) value to a thickness?)

Looking forward to some comments. thanks

joe

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