Dear Group,

With regards to the warping issues inherent with this design, do you think
that some gains could be made by increasing the core thickness for layers
5/6 thereby reducing the preg thickness between 3 and 4?  We don't play
around much with unbalanced builds so I have no practical experience to fall
back on at this moment in time.

Thanks
John Parsons

> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of John Parsons
> Sent: November 24, 2004 11:11 AM
> To: [log in to unmask]
> Subject: Re: [TN] Controlled Impedance Design
>
>
> Hmmm, tricked again!  So much for trying to get all my ducks in a
> row before
> contacting the customer.  His reply to my questions relating to his
> impedance controls design was this;
> "The board is not really an controlled impedance design. It is an IS
> (Intrinsic Safety) design. We require the 1mm clearance from the copper on
> layer 4 to the copper on the bottom layer."
>
> Thanks for all your input.
>
> Now, how to make this puppy FLAT?
>
> John
>
> > -----Original Message-----
> > From: TechNet [mailto:[log in to unmask]]On Behalf Of John Parsons
> > Sent: November 24, 2004 9:19 AM
> > To: [log in to unmask]
> > Subject: [TN] Controlled Impedance Design
> >
> >
> > This is one for the experts.  I have been under the general
> > assumption that
> > with controlled impedance designs (single ended microstrip) that the
> > reference plane is typically the first adjacent plane layer
> encountered in
> > the stack-up.  We are quoting a 6 layer build for a customer
> which has the
> > following stack-up (cap construction specified)
> > L1 Signal Layer (2oz)
> > 8mil core
> > L2 Split Plane Layer (2oz)
> > 5mil preg
> > L3 Split Plane Layer (2oz)
> > 5mil core
> > L4 Split Plane Layer (2oz)
> > 22mil preg
> > L5 Split Plane Layer (2oz)
> > 22mil core
> > L6 Signal Layer (2oz)
> > We have not built this before but they have indicated that previous
> > prototypes suffered from warping (you don't say!) and the doc's
> > state "This
> > is a controlled impedance PCB.  Spacing between L4 and L6 must be 44mil.
> >
> > My question, from a controlled impedance perspective does it
> seem to make
> > sense to spec the distance between the outer layer 6 and layer
> 4 (2 plane
> > layers away) as having a critical spacing requirement?  We have not been
> > provided with the impedance requirement nor the critical traces.
> >
> > Educate me please!
> >
> > Regards
> > John Parsons

---------------------------------------------------
Technet Mail List provided as a service by IPC using LISTSERV 1.8e
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL)
To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest
Search the archives of previous posts at: http://listserv.ipc.org/archives
Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815
-----------------------------------------------------