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November 2004

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From:
Happy Holden <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, [log in to unmask]
Date:
Wed, 24 Nov 2004 12:49:00 -0500
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Hi John,
I encountered this about a dozen years ago from a large OEM had combined a
digital board and an analog board into one.  So one side was digital
(controlled Impedance) and the other side was analog with RF sections.
Rather than give us the electrical performance they wanted they gave us
all the dimensions and tolerances and went even so far as to say that we
should use an autoclave to laminate it in.  This did not prove to be to
successful as they did not know our lamination process as well as we knew
how to make an unbalanced construction (this one had 7 layers) come out
and stay flat.  They had reference layer for signals that were not
adjacent but a couple of layers away.  They didn't realize that with the
newer Polar Impedance Solvers we could just as easily calculate the
impedance as they could.  In the end, they gave up trying to guess our
production process and described the FINAL PRODUCT and performance they
needed.  If they specify all the variables for a particular impedance they
overconstrain the design and no-one can build it.  Ask them WHAT they
really want.
Happy Holden
Westwood Associates




John Parsons <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
11/24/2004 12:19 PM
Please respond to
TechNet E-Mail Forum <[log in to unmask]>; Please respond to
John Parsons <[log in to unmask]>


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Subject
[TN] Controlled Impedance Design






This is one for the experts.  I have been under the general assumption
that
with controlled impedance designs (single ended microstrip) that the
reference plane is typically the first adjacent plane layer encountered in
the stack-up.  We are quoting a 6 layer build for a customer which has the
following stack-up (cap construction specified)
L1 Signal Layer (2oz)
8mil core
L2 Split Plane Layer (2oz)
5mil preg
L3 Split Plane Layer (2oz)
5mil core
L4 Split Plane Layer (2oz)
22mil preg
L5 Split Plane Layer (2oz)
22mil core
L6 Signal Layer (2oz)
We have not built this before but they have indicated that previous
prototypes suffered from warping (you don't say!) and the doc's state
"This
is a controlled impedance PCB.  Spacing between L4 and L6 must be 44mil.

My question, from a controlled impedance perspective does it seem to make
sense to spec the distance between the outer layer 6 and layer 4 (2 plane
layers away) as having a critical spacing requirement?  We have not been
provided with the impedance requirement nor the critical traces.

Educate me please!

Regards
John Parsons

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