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November 2004

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Subject:
From:
"Mcmaster, Michael" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Mcmaster, Michael
Date:
Tue, 16 Nov 2004 13:00:07 -0800
Content-Type:
text/plain
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text/plain (129 lines)
In addition to the part manufacturer, you should also consult with your
fabricator.

I've seen some PCB layout application notes for components that don't
necessarily take into account the best overall solution when you include the
PCB package.  Filled vias, plugged vias, plated shut vias and extra thick
copper are all potential solutions to the problem but each carries a unique
set of challenges, interactions and potential cost increases.

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Dave Seymour
Sent: Tuesday, November 16, 2004 11:06 AM
To: [log in to unmask]
Subject: Re: [TN] (QFN) Microchip Carrier with Center PAD

Scott,

First off I would check with the manf. of the part for recommendations
on layout guidelines.

When I have used this type of part in the past. There usually needs to
be multiple
vias in the heatslug area. These vias should be filled or plugged
suitable for
via in pad component mounting.

In addition the volume solder paste applied needs to be limited.
The vendor, whose part I last used,  recommend an exposed copper fill
area under
the BGA of .225x.225 with 36 vias @ .010 finished and plugged. Then also
recommended
9 openings of .036x.036 in the paste stencil. This effectively reduces
the volume of paste and does
not allow a giant dome of liquid solder to form and lift the part off
the surface during reflow.

Below is a similar part. A QFP package with heat slug.

http://www.smsc.com/main/anpdf/an119.pdf

Figure #3 show the top side gerber/copper under the part.
I believe there is a typo on the figure 8, that should read paste-mask, not
solder mask. The picture shows the concept of paste openings over the
heatslug area.

Hope this helps.

Dave


Scott Lefebvre wrote:

>        I am requesting information from the vast knowledge of this forum.
We are going to use a Gennum (QFN 16pin) package with a center thermal
ground pad.  I do not have much experience with this package.
>
>
>
>>I was going to suggest to use ENIG or Immersion Silver for the PCB finish
due to co-planarity concerns.
>>If I chose to use the board finish I mentioned, should the vias be plated
close to prevent solder scavenging during Reflow.
>>I am also concerned about the center pad surface tension, causing the part
to lift and screw during reflow,  then potentially creating opens on the
outer pads.
>>
>>
>
>
>Any help in this matter would be greatly appreciated, thanks in advance.
>
>Scott.
>
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--
Dave Seymour, CID+
Catapult Communications Inc.
800 Perimeter Park Dr, Suite A
Morrisville, NC 27560

Direct: (919)653-4249
Main: (919)653-4180
Fax: (919)653-4297

[log in to unmask]



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