TECHNET Archives

October 2004

TechNet@IPC.ORG

Options: Use Monospaced Font
Show Text Part by Default
Show All Mail Headers

Message: [<< First] [< Prev] [Next >] [Last >>]
Topic: [<< First] [< Prev] [Next >] [Last >>]
Author: [<< First] [< Prev] [Next >] [Last >>]

Print Reply
Subject:
From:
Ahne Oosterhof <[log in to unmask]>
Reply To:
Date:
Fri, 15 Oct 2004 09:28:36 -0700
Content-Type:
text/plain
Parts/Attachments:
text/plain (216 lines)
One assumption is missing: Assuming the circuit board is accurate.
It is very possible to accurately place the component next to the pad (maybe
not quite next to). My question is: how accurate do you assume the circuit
board (say 12x14 inches) is, using the fiducials as reference points.

Have fun,
Ahne.

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Ryan Grant
Sent: Friday, October 15, 2004 8:36
To: [log in to unmask]
Subject: Re: [TN] Aperture for 0603mm chip

Hi L. A. Quoc,

        Assuming pad design is not bad and component solderability is not
bad, placement accuracy is the biggest determinant of tombstones with solder
paste alignment a distant second.  You've got to be AT LEAST 0.03mm of
accuracy, which will still give some tombstones.  I've seen the newer
machines get as accurate as 0.005mm and the tombstones dropped to such a low
DPM they were no longer noticeable.  You can predict the direction of the
tombstone based on the direction of misplacement.  Or vice versa, predict
the direction of misplacement (since it is subtle) by the direction of
tombstones.
        Remember there is a normal distribution of placement accuracy, so
looking at just one or two placements won't tell you the net shift.
You'll need to look at several placements (at minimum, through a scope;
preferably with automated measuring equipment) to determine the net shift of
the distribution.  (This is basic SPC).  You'll also find both placement and
printing accuracy are worse the farther from the center of the board.  So
larger boards are more of a risk that small boards.

        One of several causes for tombstones is that one of the solder
deposits becomes liquid before the deposit on the other side of the chip
becomes liquid.  Without any surface tension to hold the opposite side down,
the chip will be pulled by the liquid solder on one side.
Anti-tombstoning solder paste is an alloy that has a pasty range so that the
transition time between solid to liquid is longer. This increases the chance
that both solder deposits will be at least partially liquid before one of
the two becomes fully liquid.  Your lead-free solder paste already has this
quality.

        By the way, I've read several studies of the wonderful qualities of
anti-tombstoning solder paste.  I've also heard of a few, "unpublished",
studies where the anti-tombstoning solder paste was no better than normal
solder paste in a DOE.  I had a psychology professor once describe this
effect for paranormal phenomenon.  The studies disproving the phenomenon are
far more numerous than studies proving the phenomenon, but they are never
published because disproving something is sooo boring.  So most of the
"published" studies concerning paranormal phenomenon indicate it is
possible.

        For me, the jury is still out on how well anti-tombstoning solder
paste works.  I do think the theory of them is correct so I would imagine it
will help; but I doubt it will "prevent" tombstones.

Ryan

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Le Ai Quoc
Sent: Thursday, October 14, 2004 8:41 PM
To: [log in to unmask]
Subject: Re: [TN] Aperture for 0603mm chip


Thank you Ioan,
The gap between the pads is 0.3mm (if it is 0.023" (0.6mm), the chip whose
length is 0.6mm could not get good wetting in all cases). The size of pad is
0.3x0.3mm. We are using Pb-free solder paste for that PCBA. With the pad
design like this, each electrode of part will sit on pad about 0.15mm in
ideal case. How big is the misalignment which is allowed for this part?
Printing result is registered well, no offsets at placement (I checked with
microscope) and we are doing the aperture 100% as pad size.
What is the ideal time for pre-heating at reflow? Now we don't get any case
of solder ball at these chips with current profile.
I heard that there are some aperture styles which can prevent this problem.
Also, I have never heard about anti-Manhattan/tombstoning solder paste, what
is that?

Thanks and best regards,
L. A. Quoc


----- Original Message -----
From: "Tempea, Ioan" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, October 14, 2004 7:54 PM
Subject: Re: [TN] Aperture for 0603mm chip


> Quoc,
>
> I don't see you mentioning land pattern design. If the gap between the
pads
> is bigger than 0.023", you start increasing your probability of
tombstoning.
> Then, in case your soldering paste (if no-clean) does not create
mid-chip
> balls, you could print 1:1, no homeplating, although we reliably do
> homeplating on 0603s that have a good pad design.
>
> After this you just check your process step by step: the printing
shall be
> well registered, no offsets at placement and yes, the reflow recipe
has an
> influence, if everything else is OK. You will need longer preheating,
to
> make sure that the paste on both pads melts at the same time when
hitting
> the spike. But a good reflow recipe will not correct poor printing or
> insertion.
>
> Also there are so called anti-tombstoning pastes out there, that are
worth
> trying.
>
> Good luck,
> Ioan
>
> > -----Original Message-----
> > From: TechNet [SMTP:[log in to unmask]] On Behalf Of Le Ai Quoc
> > Sent: Wednesday, October 13, 2004 11:32 PM
> > To:   [log in to unmask]
> > Subject:      [TN] Aperture for 0603mm chip
> >
> > Hi Technetters,
> > Do you know the opening style (aperture) for stencil (metal mask)
applied
> > for printing solder paste on resistance, capacitor chip 0603mmm to
prevent
> > "Tombstone/Manhattan" after reflow. Also, pls. advise about stencil
> > thickness.
> > Last but not least, is the reflow profile important for this defect?
Any
> > suggestion?
> > Thanks in advance,
> > Le Ai Quoc
> >
> > ---------------------------------------------------
> > Technet Mail List provided as a service by IPC using LISTSERV 1.8e
> > To unsubscribe, send a message to [log in to unmask] with following
text
in
> > the BODY (NOT the subject field): SIGNOFF Technet To temporarily
> > halt or (re-start) delivery of Technet send e-mail to
> > [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE
> > mailing per day of all the posts: send e-mail to
> > [log in to unmask]: SET Technet Digest Search the archives of previous
> > posts at:
http://listserv.ipc.org/archives
> > Please visit IPC web site
http://www.ipc.org/contentpage.asp?Pageid=4.3.16
> > for additional information, or contact Keach Sasamori at
[log in to unmask]
or
> > 847-509-9700 ext.5315
> > -----------------------------------------------------
>
> ---------------------------------------------------
> Technet Mail List provided as a service by IPC using LISTSERV 1.8e To
> unsubscribe, send a message to [log in to unmask] with following text
in
> the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt
> or (re-start) delivery of Technet send e-mail to
[log in to unmask]: SET Technet NOMAIL or (MAIL)
> To receive ONE mailing per day of all the posts: send e-mail to
[log in to unmask]: SET Technet Digest
> Search the archives of previous posts at:
http://listserv.ipc.org/archives
> Please visit IPC web site
http://www.ipc.org/contentpage.asp?Pageid=4.3.16
for additional information, or contact Keach Sasamori at [log in to unmask] or
847-509-9700 ext.5315
> -----------------------------------------------------
>

---------------------------------------------------
Technet Mail List provided as a service by IPC using LISTSERV 1.8e To
unsubscribe, send a message to [log in to unmask] with following text in the
BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or
(re-start) delivery of Technet send e-mail to
[log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per
day of all the posts: send e-mail to
[log in to unmask]: SET Technet Digest
Search the archives of previous posts at:
http://listserv.ipc.org/archives
Please visit IPC web site
http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information,
or contact Keach Sasamori at [log in to unmask] or 847-615-7100
ext.2815
-----------------------------------------------------

---------------------------------------------------
Technet Mail List provided as a service by IPC using LISTSERV 1.8e To
unsubscribe, send a message to [log in to unmask] with following text in the
BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or
(re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet
NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send
e-mail to [log in to unmask]: SET Technet Digest Search the archives of
previous posts at: http://listserv.ipc.org/archives Please visit IPC web
site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional
information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100
ext.2815
-----------------------------------------------------

---------------------------------------------------
Technet Mail List provided as a service by IPC using LISTSERV 1.8e
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL)
To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest
Search the archives of previous posts at: http://listserv.ipc.org/archives
Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815
-----------------------------------------------------

ATOM RSS1 RSS2