Geoff:
Yes we are routing the castellation holes after electroless. We understood
that if we did after plating we will have more burrs but I will look into
these special routers. Can I have HP-Tec's number. I did google search but
they may not have a website.
Thanks
Sona

----- Original Message -----
From: "Geoff Layhe" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, October 12, 2004 12:06 PM
Subject: Re: [TN] Castellation boards


> Are you routing through the castellated holes after electroless?
> It might be better if you plated all the hole and only routed through to
> form the castellations at the end. There are special routers available
which
> will do the job, I know that HP-Tec have one and there are probably
others.
>
> hope this helps
> Geoff Layhe
> Lamar Group
>
> -----Original Message-----
> From: Fineline Circuits, Inc. [mailto:[log in to unmask]]
> Sent: Tuesday, October 12, 2004 3:59 PM
> To: [log in to unmask]
> Subject: [TN] Castellation boards
>
>
> I would like to know how to accomplish burr free plated castellation tab
> routing and or scoring.
> We are seeing plating slivers coming off during masking. Our process is
> drill, electroless, tab route array, copper flash, image , second plate
> copper and tinlead, etch, mask and route array. The design is such that
> copper extends all the way to the edge of the board. Tab routing after
> electroless we see a burr free edge but after strike and second plate, the
> copper foil on the edge gets overplated and when we go to mask we run into
> sliver  problems. Even if we recess the copper a bit from the edge of the
> board (5mls) than  in imaging we are having problems for the 5ml laminar
to
> adhere to the edge of the board after developing.
> Material is FR4.
> Appreciate your input.
> Sona Sitapara
>
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