Sona,
If your not using the inital tab array to give plated edges,(and as your
doing this after electroless, it appears so), then why not just perform the
tab array at the same tine as the final profile, thus giving a clean and
relatively burr free edge. Correct routing speeds and feeds along with good
tool cutting edges and vacumn should be adequate for this.

Regards,

Colin McVean

Circuit Manufacture Ltd
Unit 9-12
Rowleys Green Lane
Longford
Coventry
CV6 6AG

Tel: 02476 666168
Fax: 02476 637089
n any attached files using your own anti-
virus software.


-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Fineline Circuits,
Inc.
Sent: 12 October 2004 15:59
To: [log in to unmask]
Subject: [TN] Castellation boards


I would like to know how to accomplish burr free plated castellation tab
routing and or scoring.
We are seeing plating slivers coming off during masking. Our process is
drill, electroless, tab route array, copper flash, image , second plate
copper and tinlead, etch, mask and route array. The design is such that
copper extends all the way to the edge of the board. Tab routing after
electroless we see a burr free edge but after strike and second plate, the
copper foil on the edge gets overplated and when we go to mask we run into
sliver  problems. Even if we recess the copper a bit from the edge of the
board (5mls) than  in imaging we are having problems for the 5ml laminar to
adhere to the edge of the board after developing.
Material is FR4.
Appreciate your input.
Sona Sitapara

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