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October 2004

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Subject:
From:
Paul Edwards <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Paul Edwards <[log in to unmask]>
Date:
Sat, 9 Oct 2004 11:29:13 -0700
Content-Type:
text/plain
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text/plain (194 lines)
Ofer,

When you stencil paste into the vias, with the proper profile, they will
limit the amount of solder that actually will flow down the hole, ASSUMING
of course that the solder paste is actually touching and will wet the
backside of the IC.

We thermally bias the profile to limit the solder movement in the vias
during reflow.

If you can't do this you play the "diameter-to-depth" ratio verses stencil
thickness game.

Paul

Paul Edwards
Process Engineering
[log in to unmask]
Tel: 408-433-4700
FAX: 408-433-9988
Surface Art Engineering
81Bonaventura Dr.
San Jose, CA 95134
DUNS: 944740570
CAGE/NCAGE: 1XZ48

-----Original Message-----
From: Ofer Cohen [mailto:[log in to unmask]]
Sent: Thursday, October 07, 2004 9:18 PM
To: TechNet E-Mail Forum; Paul Edwards
Subject: RE: [TN] Solder pad under chip

Paul,
If drilling vias in the pad then, due to capillarity forces, the paste will
be suck into the vias. We had such a problem in a grounded pad, and we had
to design the paste aperture in the stencil so there will not be paste
aplication to the vias areas.

Regards
Ofer Cohen
Manager
Quality Assurance, Reliability and Production Technologies
SEABRIDGE Ltd. - A Siemens Company

> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Paul Edwards
> Sent: Tuesday, October 05, 2004 20:01
> To: [log in to unmask]
> Subject: Re: [TN] Solder pad under chip
>
>
> If you want to eliminate the voiding issue and have a quick
> check if the
> part is soldered...try putting some vias in the grnd
> pad....Make sure you
> get solder into the vias...3 to 4 mils of solder in the vias should
> compensate electrically and thermally for the missing copper
> generated by
> the holes...
>
> Paul Edwards
> Process Engineering
> [log in to unmask]
> Tel: 408-433-4700
> FAX: 408-433-9988
> Surface Art Engineering
> 81Bonaventura Dr.
> San Jose, CA 95134
> DUNS: 944740570
> CAGE/NCAGE: 1XZ48
>
> -----Original Message-----
> From: Jason Gregory [mailto:[log in to unmask]]
> Sent: Tuesday, October 05, 2004 6:16 AM
> To: [log in to unmask]
> Subject: Re: [TN] Solder pad under chip
>
> Sounds like possibly the pad was not in the solder paste
> layer and wasn't
> cut. As far as inspecting, I had to do this in a former life.
> We inspected
> the pad with a 5DX, but not just for the presence of solder,
> but for solder
> coverage percentage. It was in the specs to ensure 70% solder
> coverage. I
> also learned alot about vacuolar porosity. You might want to inspect a
> sample every 10 boards or so with X-ray.....if you have the ability.
>
>
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Bob Wilson
> Sent: Monday, October 04, 2004 3:01 PM
> To: [log in to unmask]
> Subject: [TN] Solder pad under chip
>
>
> Hi!
>
> I have a chip on a board (Linear Technology part
> number LTC3414) found here:
> http://www.linear.com/pdf/3414f.pdf
>
> It has a pad (pin number 21) that is underneath and a
> note that says: "To maximize the thermal performance
> of the LTC3414, the exposed pad should be soldered to
> a ground plane."
>
> I built the footprint and made sure the pad was
> soldermasked and included the pad shape in the
> pastemask file.
>
> The engineer was trouble-shooting and de-soldered the
> part from the board.  It looks like there was no
> solderpaste or solder on the pad.
>
> Here's the (dumb) designer question:  How would the
> solder get to that pad underneath? Should we add a
> requirement note saying that the part should be
> inspected or x-rayed to see if the pad is indeed
> soldered?
>
> Thanks for all and any suggestions.
>
> Regards,
>
> Bob Wilson
> www.cstone-design.com
> [log in to unmask]
>
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