Colleagues,
Here is the schedule for the Embedded Passive activities taking place at
IPCWorks 2004 next week in Minneapolis, NN within the Minneapolis
Convention Center:
Monday, October 25, 2004
1:30 pm - 5:00 pm
Room 204A
D-37d Embedded Passives Test Methods Task Group
Tuesday, October 26 2004
8:00 am - 5:00 pm
Room 204A
D-37b Embedded Passives Materials Task Group (IPC-4811 and IPC-4821)
(Please note this meeting has been extended to 5:00 pm)
Wednesday, October 27, 2004
8:00 am - 10:00 am
Room 201A
D-37a Embedded Passives Design Task Group (IPC-2316)
(Please note this is a meeting time and date change from the original
10/25/04 8:00 AM slot)
Thursday, October 28, 2004
9:00 am - 3:00 pm
Room 204AB
S-01 Design Challenges Technical Paper session
This technical paper session will feature 3 papers related to embedded
passives, including
* Barriers to Implementation of High Performance Embedded
Capacitance Laminates
* Joel Pfeiffer, 3M Company
* Designing Resistors to Embedded
* Richard Snogren, Coretec Denver, Inc.
* PWB Design: Beyond Copper Interconnects
* Robert Croswell, Motorola Inc.
Thursday, October 28, 2004
1:30 pm - 4:30 pm
Room 205B
S-04 ECIT - Emerging/Critical Interconnect Technology Overview Session
Jason Ferguson of NSWC-Crane will present an Embedded Passives Status
within this technical session
Regards,
John Perry
Technical Project Manager
IPC
3000 Lakeside Drive # 309S
Bannockburn, IL 60015
[log in to unmask]
1-847-597-2818 (P)
1-847-615-7105 (F)
1-847-615-7100 (Main)
Get Ready to Work at IPCWorks 2004 - www.ipc.org/IPCWorks2004
|
