Hi Thomas,

My first guess is that it is laminate imperfection. If there is a laminate
void between the two shorted layers; the gap between the two layers may go
below 3 mil and cause the low resistance and the eventual short. I do not
think the warpage (bow) or the type of service finish have to do with the
root cause of the problem. However the use of Polyimide laminate which,
normally, has higher water absorption may have contributed to the problem.

It is important to cross section a failed board where the short occurs (do
not destroy the evidences by running current through the board). Most
probably you will see a laminate void and reduced gap.

Sherif Refaat, Eng.
Technology Roadmap Consultants Inc.



----- Original Message -----
From: "Himel, Thomas M." <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, September 24, 2004 4:59 PM
Subject: [TN] PWB interlayer short problem


We are having trouble with a PC board produced for us developing a short
between two planes in two adjacent layers.  The very worrying thing is that
this short usually doesn't occur until the board has been run for many
hours.   I'd appreciate advice on the following questions:
1.      What is the likely root cause of the problem and why?
2.      Is there a test we can do on unloaded boards to find the incipient
problems?
3.      Is there a test we can do on loaded boards to find the incipient
problems?
4.      What tests should we do on a failed board to help us determine the
root cause of the problem?
5.      What are the likely design/process problems that lead to these
failures?
6.      Is there a process change we can do to prevent future problems?
I know this is a tall order and that you need to know lots about the board
design and the problem to even begin to help.  I'll do my best to give
enough information and then respond to questions anyone might have.  We are
under both a budget and schedule crunch and cannot tolerate failures after
the boards are put in the final product so I really appreciate any help any
of you can give.
1.      It is an eight layer PWB with dimensions about 1 by 12 inches.
        2.      It is stacked up from a copper foil, 3 double sided boards
and then a copper foil.  Separating the parts are 3 mil Arlon 35N polyimide
/ E-glass two ply  prepreg sheets.
        3.      The short occurs between one of the outside copper foils and
the copper of the adjacent double layer board (separated by the 3 mil
prepreg).
        4.      Both of these layers are essentially planes.  One normally
has 120 VDC on it and the other a few volts.
        5.      We have built 850 bare boards, loaded 300 and burned in 208
of those.  We need 700 good boards.
        6.      A flying probe test on the 850 bare boards at 250 V found no
shorts between the two layers.
        7.      3 (of the 300) loaded boards had a short between the two
layers immediately after being loaded.  All other boards held 200 volts in
two separate tests that are done after loading and before burn-in.
        8.      6 (of the 208) boards developed a short during burn in at 85
degrees C with 120 V applied. They failed after about 4, 6, 10, 18, 25, and
75 hours of a 200 hour burn-in.  The 120 V is applied through a 270 k Ohm
resistor in the circuit which limits the current to 0.4 mA.
        9.      Calling them "shorts" is over-simplified.  The 6 boards
develop a low resistance between the two layers.  This resistance can go up
and down some, but gradually gets less as time and current pass by.
        10.     To localize the problem on the 6 boards that failed during
burn-in we used a lab supply to run higher currents between the layers.
Running over an amp through each board caused the problem area to heat up
and ultimately blister.  The blisters are not near vias and are in different
locations on each board.
        11.     One of these boards we sectioned and polished.  This reveals
a void and crack in the prepreg layer.  We assume we caused this by running
the high current through it and that we destroyed any evidence of the root
cause.
        12.     Moisture has been suggested as a possible culprit, here are
a few relevant facts
a.      The bare boards are stored in uncontrolled California conditions for
several months before being loaded.  They are not in moisture barrier bags
and the average humidity in the area is 35%.
                        b.      Before being loaded the boards are stored
for a  couple of weeks in a dry closet at the company where they are loaded.
They are not baked prior to reflow soldering.
13.     The boards are reflow soldered with lead based solder.  All the
components are surface mount.  A rosin based solder paste is used that meets
IPC J standard 006. The part is cleaned in water and alcohol.
        14.     The board did not go through a HASL (Hot Air Solder
Leveling) process.
        15.     The bare board bows by about 1 mm.
        16.     The loaded board bows by several mm.
        17.     The total board thickness is 34 mils.
        18.     The IPC standard for dielectric thickness for 101-150 volts
is 8 mils.  We have used 3 but believe it is common to do this.  The
breakdown voltage for a 3 mil air gap is 225 volts.  For 3 mils of polyimide
it is about 3 kV.
My email address is thimel AT slac.stanford.edu

Thanks for any help or information you can provide.



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