I have been doing some interesting work in the area of lead free solder
laminate, it shows the typical vias lack of ability to withstand repeated
thermal cycles before cracking, is one of the big problems. I pulled out a
old high reliability process that I invented years ago and ran tests with a
HATS tester on 135 t/g material which is better suited to lead free temps
then the 170 t/g. I got 2000 hats cycles after 6 x solder float simulation
on a 6 layer board ( typical is 120 to 300 cycles)
It ran 380 deg f for 12hours with out damage and survived 30 solder floats
( the laminate was dark brown but the vias were not cracked. next I let
samples sit for 1,2,3,4 and 5 miniuts at 550 c and again no cracked vias,
the 4 and 5 minuits laminate was damaged but the vias were ok. If any one
is interested in testing on a lead free board this process please contact
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