Dear all,
Some comments on Annealing (developed, introduced and promoted by E4, which is Infineon Technologies, Philips Semiconductors, STMicroelectronics, Freescale Semiconductors)
1. Annealing is not a test, but a mitigation strategy to prevent whisker formation
2. We prefer the word "bake", since annealing is an effect of second order. Yes, recristallisation, dislocation slide and climb, recombination and all these effects take place at 150 °C and result in a stress relieve (if there is any stress prior to the baking), but the major effect is the artificial growth of the intermetallic double layer Cu3Sn / Cu6Sn5 at the Cu -Sn interface. This intermetallic layer grows regularly at 150 °C and forms a continuous layer, which acts as a diffusion barrier for further Cu-diffusion into tin. This Cu- diffusion is associated with the intermetallic formation and happens only in the tin grain boundaries at RT (--> irregulargroth of intermetallics), but due to a shift from grain boundary diffusion in favour of bulk diffusion at higher temperatures at 150 °C, the layer is formed regularly. Since the intermetllic formation is associated with a volume increase, the irregularities induce stress and have to be avoided. This can be done by the introduction of addtional diffusion barrier matals (Ni, Ag, ...) or by the artificaial growth of the intermetallic itself.
Thus bake can only be applied to Cu-based leadframes without additional underlayer such as Ni or Ag or something else. It is also not applicable to FeNi42 L/F since the mechanism for whisker formation is different (stress induction during thermal cycling due to large cte mismatch of FeNi42 and Sn) and also the intermetallics are different also the growth rate differs significantly.
Infineon does not make any difference in accordance to the pitch, but applies 150 °C / 1h post plate bake to all components with Cu L/F and matt pure tin plating.
please find some of our publications on this issue for download at our website
http://www.infineon.com/cgi/ecrm.dll/jsp/showfrontend.do?lang=EN&channel_oid=-11663
More publications and info available on request.
regards,
Marc Dittes, Infineon Technologies
-----Ursprüngliche Nachricht-----
Von: Leadfree [mailto:[log in to unmask]] Im Auftrag von Victor G. Hernandez
Gesendet: Mittwoch, 14. Juli 2004 13:03
An: [log in to unmask]
Betreff: Re: [LF] Whisker test
Fellow TechNetter:
Can someone share their understanding of the annealing process of metals.
Victor,
-----Original Message-----
From: Leadfree [mailto:[log in to unmask]] On Behalf Of Gupta, Munish
Sent: Wednesday, July 14, 2004 3:46 AM
To: [log in to unmask]
Subject: [LF] Whisker test
14 july 04
Need expert inputs only...
Is whisker mitigation strategy* applicable for all packages.
A big package like TO220 where leads are seperated by a large distance (much greater than what a typical length of whisker is
:
50um) should NOT undergo special tests like annealing.
Annealing is time as well as energy consuming.
*: bake for 150C @ 1hr
advised by ST , Philips , Infenion
Any comments TONY ! ! !
regards
munish
INDIA
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To temporarily stop delivery of Leadree for vacation breaks send: SET Leadfree NOMAIL
Search previous postings at: http://listserv.ipc.org/archives
Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
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