Dear TechNetters,

Please can anyone point me to any specification covering the coplanarity of
the footprints on the PCB surface?

I've looked in IPC-A-600F and IPC-6010 series, and, whilst flatness in terms
of bow and twist is specified, there does not appear to be anything
regarding the coplanarity across a component footprint. I have a current
design where the use of thin dielectrics  fear may tend to ape the copper
topography on the underlying layers (they are predominantly tracks rather
than planes). The footprints happen to be BGA, CGA and QFP for ceramic
packages and whilst I have not yet received the boards they are to be
assembled to, I would like to be aware if I should do measurements and to
what limits are acceptable on receipt. I am concerned excessive undulation
may give some soldering issues with opens but don't know if my concerns are
unfounded.

I believe various studies and consortia have measured surface coplanarity in
the past during studies into soldering processes etc, but unfortunately I
lost touch with the conclusions due to an outsourcing strategy of a big OEM.
Maybe these concluded that board coplanarity is not an issue but if anyone
can help reassure me, particularly regarding flex rigid PCBs with thin
dielectrics, or if anyone has previous experience in this area you could
share, I'd be very grateful.

Many thanks in advance.

Phil Anslow.


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