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Date: | Tue, 22 Jun 2004 22:11:05 +0200 |
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Hi Dave,
The relevant EIA spec is available from this location:
http://www.chipro.com/PDF%20Files/EIA-481-B.pdf
Best regards,
Daan Terstegge
http://www.smtinfo.net
----- Original Message -----
From: "Dave Chapman" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, June 21, 2004 5:34 PM
Subject: Re: [TN] Component packaging
> -----Original Message-----
> From: Dave Chapman [log in to unmask]
> Sent: Monday, June 21, 2004 10:19 AM
> To: [log in to unmask]
> Subject: [TN] Component packaging
>
> Is there a IPC, JEDEC or EIA document that references how ICs should be
> packaged when on tape and reel? Specifically pin 1 locations or package
> angle as we know it in SMT. I've been through ANSI/IPC-SM780 (March of
1998)
> but not much there.
> Dave Chapman
>
>
>
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847-509-9700 ext.5315
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---------------------------------------------------
Technet Mail List provided as a service by IPC using LISTSERV 1.8e
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL)
To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest
Search the archives of previous posts at: http://listserv.ipc.org/archives
Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
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