Hi Glenn,
Digging in the archives....hmmm
According to MIL-P-13949/4C for FR4 material, The Electric Strength,
(perpendicular to laminations), average, minimum volts/mil = 750 V per mil
(.001) which is 29.25Kv per mm as one millimeter = .039 inches.
I believe this has not changed over the years. It has been my guide for
designing boards for years. A good design would de-rate by 50% and allow for
tolerances.
All of the Woven E-Glass materials in IPC-4101 call out 30Kv/mm for cores
that are less than .0197 thick, a direct take from the Mil-P-13949 spec for
'Electric Strength'.
I don't know if anyone has done some demonstrations of this, however, If I
was tasked with this and was concerned about verifying the results, I would
include a test coupon on my boards and require the board vendor to test lots
to verify that the boards pass the voltage requirement. A couple of areas
on the panel that were an example of the circuit configuration would be a
good test case and allow non-destructive testing outside the bare board
area.
Cheers,
Bill Brooks
PCB Design Engineer , C.I.D., C.I.I.
Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510
-----Original Message-----
From: Glenn Ball [mailto:[log in to unmask]]
Sent: Thursday, April 15, 2004 7:16 AM
To: [log in to unmask]
Subject: [TN] dielectric breakdown between layers (Z-axis)
Hi,
I have a design that has 270VDC between 2 adjacent layers in a 16 layer
IPC-4101/40 (polyimid) PWB. This is a high rel application and we are
designing the board for 500VDC to allow for some margin. IPC-2221
section 6.3 specifies that layer to layer spacings (dielectric
thicknesses) are to be per table 6-1 (Electrical Cunductor Spacing).
This is a change from IPC-D-275 section 3.5.3 which does not state that
table 3-1 is applicable for layer to layer spacings.
1- Does anyone know if there is a good basis for this change between
IPC-D-275 and IPC-2221?
I have read through the archives regarding this subject and the figure
of 50V/mil (.001 inch) is quoted several times for layer to layer
spacings, which is much less than the dielectric strength shown in
IPC-2221 Table 4-1 and in IPC-4101/40. In several of the postings this
10X derating of the dielectric strength is based on experiences with
failures in single sheet prepregs and/or laminates. Some postings
surmise this is a result of voids in the material. I would assume that
the possibility of a void appearing in exactly the same locations in 2
sheets of dielectric vs.1 sheet would be greatly reduced.
2 - Does anyone have experience with layer to layer voltage gradients of
greater than 50V/mil (or 500VDC max across .003-.005" dielectric) using
2 thin layers of prepreg or laminate constructed from 2 sheets of
dielectric rather than single sheets only? If so please mention what
your material is in your response.
This adjacent layer situation occurs several times in the stackup of
this board. Due to thickness constraints the layer to layer spacing of
this board needs to be around .004"-.005" so 2 106 sheets or 1 106 + 1
1080 sheet would be what we are looking at for dielectric between the
high voltage layers.
Some past postings for reference:
http://listserv.ipc.org/scripts/wa.exe?A2=ind96&L=technet&P=R39153&I=-3
http://listserv.ipc.org/scripts/wa.exe?A2=ind96&L=technet&P=R39061&I=-3
http://listserv.ipc.org/scripts/wa.exe?A2=ind9808&L=technet&P=R48036&I=-3
Thanks for the help,
Glenn
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