Hello,
With reference to IPC-2221A Table 6-1 Electrical Conductor Spacing. This
table is grouped into Bare Board B1, B2, B3, B4 and Assembly A5, A6, A7
B1 = internal conductors
B2 = External conductors, uncoated, sea level to 3050m (10007 feet)
B3 = External conductors, uncoated, over 3050m (10007 feet)
B4 = External conductors, with permanent polymer coating (any elevation)
A5 = External conductors with conformal coating over assembly (any
elevation)
A6 = External component lead/termination uncoated, sea level to 3050m
(10007 feet)
A7 = External component lead termination with conformal coating (any
elevation)
I have a design with 60V requirement. Instead of using a power
connector, 4 pads are used, two pads for 60V and the other two as its
return. On the design, the 60V pads are area fill on the internal layer
while the return pads are area fill on the external layer. The clearance
between the fill and pads are 15mil. The board is mounted and the 4
pads are soldered with AWG14 wire (multistrands). During test, arc
appeared between the 60V and return and resulted a short-circuit.
The 4 pads footprint has been used in all its previous iterations with
the same clearance of 15 mil. Those boards are mounted and tested with
no arcing.
I was told that the reason for my arcing is because the 15mil clearance
is less than the specified A6 = 0.5mm (20mil). I have not have any
arcing on those past iterations does not mean that the 15mil is
sufficient. It could be just plan luck.
1. What is your opinion and comment on this clearance?
2. When bare boards B1 to B4 are used as it does not make sense to
design a circuit board without mounting.
3. How is sea level measure or indicated?
4. As most of the boards are conformal coated first before ESS tests, if
A7 is not used but A6, would it be over-kill?
I know the message is a bit too long, but I am just curious and confuse.
Hope someone can englighten me.
Thanks and regards,
Wee Mei
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