Could you please elaborate further on your statement "Given what's coming
out about voids now....." Is there new research showing better/worse
reliability for larger voids?
Looking forward to more information.
Pete Barton
===== Original Message from [log in to unmask] (TechNet E-Mail Forum.) at
11/03/04 19:03
>Joe
>
>I was on the AT&T group that did some VIP for BGAs. We produced what we
>called "lead balloons." Mostly just BIG single voids. (Bob's point about
>height is also well taken.)
>
>They were so dramatic looking we didn't reliability test them.
>
>Given what's coming out about voids now I wish we would have! I think it was
>a great (and lost) opportunity to look a extreme voids and telecom
>reliability.
>
>Greg
>
>
>-----Original Message-----
>From: Furrow, Robert Gordon (Bob) [mailto:[log in to unmask]]
>Sent: Thursday, March 11, 2004 10:42 AM
>To: [log in to unmask]
>Subject: Re: [TN] Reliability of via in pad
>
>
>Joe,
>
>Fortunately we have no experience with VIP on BGA or CSP pads. Due to
>concerns about solder joint height we never allowed VIPs in those pads.
>
>Thanks,
>Robert Furrow
>Printed Circuit Board Engineer
>Supply Chain Networks
>Lucent Technologies
>978-682-2260 [log in to unmask]
>
>
>-----Original Message-----
>From: Macko, Joe @ IEC [mailto:[log in to unmask]]
>Sent: Thursday, March 11, 2004 1:33 PM
>To: 'TechNet E-Mail Forum.'; 'Furrow, Robert Gordon (Bob)'
>Subject: RE: [TN] Reliability of via in pad
>
>
>Robert,
>
>What has been your experience with VIP for BGA pads? I have seen them
>contribute significantly to voiding. Look forward to your response.
>
>joe
>
>-----Original Message-----
>From: Furrow, Robert Gordon (Bob) [mailto:[log in to unmask]]
>Sent: Thursday, March 11, 2004 10:15 AM
>To: [log in to unmask]
>Subject: Re: [TN] Reliability of via in pad
>
>
>Hi Ioan,
>
>We have designed boards with via in pad (VIP) for well over a decade and
>assuming you have a good solder joint, reliability in Telecom product has
>not been a problem. We did not evaluate for automotive applications. Having
>said that, let me also say that VIP is great for the designer but a royal
>pain for the assembler. It was only intended for designs where absolutely
>necessary, but it quickly got out of hand when designers realized that by
>checking off "yes" to VIP, the computer time required to route a board was
>significantly reduced. It essentially became a defacto standard on many of
>our designs. Some lessons learned were that you need to carefully control
>the finished holes size. If you specify a 10 mil nominal finished hole there
>is a world of difference between a 13 mil received and one that is truly 10
>mils. Also, as discrete sizes get to 0603 you need to require a smaller
>finished hole. We used enlarged stencil openings as well as step stencils in
>order to get the n!
> eeded solder paste applied. Another issue is to make sure that the via is
>not shared on both sides of the board with discretes or other surface mount
>pads. I would be glad to discuss further offline if you have additional
>questions or comments. We also did some work with plugging the vias, but
>found it not to be necessary if the surface mount process was optimized, so
>the cost wasn't justified. It is a slippery slope, as once you get
>proficient at one set of pad sizes, the designers are going to want to
>expand the use of VIP to other sizes and feature types.
>
>Thanks,
>Robert Furrow
>Printed Circuit Board Engineer
>Supply Chain Networks
>Lucent Technologies
>978-682-2260 [log in to unmask]
>
>
>-----Original Message-----
>From: Tempea, Ioan [mailto:[log in to unmask]]
>Sent: Thursday, March 11, 2004 8:30 AM
>To: [log in to unmask]
>Subject: [TN] Reliability of via in pad
>
>
>Hi Technos,
>
>I've got an annoying one. I am looking at an assembly for automotive, which
>has 100+ SMT resistor and capacitor pads with vias in them, on both sides of
>the 9 layer PCB. Now, I know that I will expect solder starvation, since the
>solder will flow into the via. I could eventually patch this by plugging the
>vias on the opposite sides of the concerned pads and make slightly bigger
>apertures in the stencil. Or even charge more and touch-up all the opens.
>
>But what does via in pad mean in terms of reliability?
>
>1. There will be voids, which are going to become even more important on
>lead-free (the customer is after the european market). Any reliability
>concerns related to that? Once again, I'm talking automotive.
>
>2. PTH reliability. 100+ vias will have totally random quantities of solder
>in them. I remember one of Werner's contributions (Entschuldigung Herr
>Engelmeier, aber... I lost the e-mail) saying that less than 50% fill
>degrades the reliability. Am I right?
>
>A good fix would be, in case they refuse to re-spin the board and move the
>vias, to fill the holes. What kind of specification should I issue for
>filling, in terms of material and fill percentage?
>
>Any other concerns?
>
>Thanks,
>Ioan
>
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Peter Barton
Senior Process Eng
ACW Technology Ltd
Dinas Isaf West
Tonypandy
Mid Glamorgan. CF40 1XX Wales
Tel: 01443 425200
Fax: 023 8048 4882
International Tel : +44 1443 425200
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