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Tuesday March 9th, 2004

Enabling Technologies for High Performance Chip Scale Packaging

 

Time: 6:00 -- 6:20 PM -- Food and Drink (*Better than just Pizza this time!!!!)

6:20 -- 6:30 PM -- Introduction and announcements

6:30 -- 8:00 PM -- Presentation

8:00 -- 8:30 PM -- QnA and *Door Prizes !!!! 

*Sponsored by:  -- DDI - Spectrum Marketing Associates


--------------- !! NOTE NORMAL GDDS MEETING LOCATION !! ------------------------------

Place: 

General Dynamics Decision Systems<?xml:namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" />

8201 E. McDowell Road

Scottsdale, AZ

 <http://www.mapquest.com/maps/map.adp?country=US&addtohistory=&address=8201+e+mcdowell+rd&city=scottsdale&state=az&zipcode=&homesubmit.x=30&homesubmit.y=12> View Map 


Presentation Description 

Enabling Technologies for High Performance Chip Scale Packaging

Increasing signal speeds and the migration of array packages to 0.8m and ultimately down to 0.5mm pitch are testing the limits of conventional printed circuit technologies.  The implications are significant to both the design and manufacture of next generation PWB's, since the introduction of no one new technology will address all the issues.  Instead, an array of enabling technologies will be required to work in concert, to address both signal integrity and the ever increasing interconnect densities associated with chip scale packaging.  This presentation will explore the challenges of chip scale packaging and present a production viable solution that will address materials, high aspect ratio plating, advanced imaging and registration techniques,  all required to produce next generation stacked microvia structures.   
 
 
About the Presenter
Tom Buck
Director Technical Marketing 
Dynamic Details Inc.

Tom has over twenty five years experience in the field of custom designed high performance electronic interconnection products designed primarily for telecommunications high end commercial computing and advanced military systems.  Extensive experience in the design and manufacture of high speed/ high density digital packaging with interconnect products including , Multichip Modules both deposited and laminated, high density Multilayer Circuits and advanced projects including monolithic electro-optic circuits.  Other activities have included:  Conducting technical seminars on high speed circuit design throughout the United States and Europe, authored many technical articles published in industry trade journals and presented numerous technical papers at industry conferences.  

 

PLEASE RSVP NO LATER THAN Monday March 8th, 2004 

Cyrus Ringle CID +
IPC Advanced Certified Interconnect Designer
CAD Engineer
Inter-Tel, Inc.  <http://www.inter-tel.com/> http://www.inter-tel.com
7300 W. Boston St.
Chandler, AZ 85226
(480) 961-2263
mailto:[log in to unmask]

President of the Greater Phoenix Designers Council
 <http://dcchapters.ipc.org/phoenix/> http://dcchapters.ipc.org/phoenix/


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Cyrus Ringle CID +
IPC Advanced Certified Interconnect Designer

CAD Engineer
Inter-Tel, Inc.  <http://www.inter-tel.com/> http://www.inter-tel.com
7300 W. Boston St.
Chandler, AZ 85226
(480) 961-2263
mailto:[log in to unmask]

President of the Greater Phoenix Designers Council
 <http://dcchapters.ipc.org/phoenix/> http://dcchapters.ipc.org/phoenix/


 

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