To expand on this topic, is there a minimum spacing from a chip to board
edge? How about large chips, 2512?
-----Original Message-----
From: Bruce D Stilmack [mailto:[log in to unmask]]
Sent: Wednesday, January 07, 2004 10:54 AM
To: [log in to unmask]
Subject: Re: [TN] CC Mechanical stress
George I was about to mention the same thing. We had this same problem on
some boards. The CCA's were 5 to a panel and when you broke them out, the
caps on the edges of the boards (the edges that were shared) would usually
crack. After change to parallel, we had zero cracks.
Bruce Stilmack
GDLS-TO Manufacturing Engineer
(850) 574-4773
[log in to unmask]
"Wenger, George
M." To: [log in to unmask]
<George.Wenger@A cc:
NDREW.COM> Subject: Re: [TN] CC
Mechanical stress
Sent by: TechNet
<[log in to unmask]
>
01/06/2004 11:56
AM
Please respond
to "TechNet
E-Mail Forum.";
Please respond
to "Wenger,
George M."
Werner,
I agree. I forgot to mention the solder fillet reduction. I also forgot
to indicate that our other internal requirment is to mount ceramic chip
capacitors with their long axis parallel rather than perpendicular to the
nearest edge.
Regards,
George
George M. Wenger (908)-546-4531
Reliability Engineer
RF Power Amplifier Group
Andrew Corporation, 40 Technology Drive, Warren, NJ 07059
[log in to unmask]
-----Original Message-----
From: Werner Engelmaier [mailto:[log in to unmask]]
Sent: Tuesday, January 06, 2004 11:38 AM
To: [log in to unmask]
Subject: Re: [TN] CC Mechanical stress
Hi,
George gave good advice. A further measure is to REDUCE the size of the
solder fillets--large solder fillets act like vise-grips during
high-strain-rate
loading such as riveting and depanelizing. Large solder fillets serve no
real
purpose for samall CC's.
Regards,
Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL 32174 USA
Phone: 386-437-8747, Fax: 386-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com
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