Would orientation make a difference on the survival rate? It seems
to me that if the caps are oriented along the smallest side of the board
there will be less stress on them. Any thoughts?
Ramon
> -----Original Message-----
> From: Dale Ritzen [SMTP:[log in to unmask]]
> Sent: Tuesday, January 06, 2004 10:27 AM
> To: [log in to unmask]
> Subject: Re: [TN] Ceramic Capacitor Board Edge Clearance
>
> Richard,
> Be careful here... We also had a cracked capacitor issue with one of our
> customer's boards in exactly the same scenario which you described. After
> working with the customer and fighting the problem for several months, we
> tried a different capacitor vendor (not a different size device), and
> voila... The problem mysteriously went away. Imagine that! So, we have to
be
> really careful just where we point the gun in this type of a situation.
>
> This type of failure is a "bugger" to find, especially if a functional
test
> won't find them (normally they don't). Of course, placing the caps farther
> from the board edge could significantly increase their chance of survival
> when being cut apart with a "pizza cutter". Someone (I want to say TRW)
has
> a pretty good "white paper" on this. When we were working with our
customer
> I forwarded the paper to them and they did modify their board design in
the
> next iteration to avoid the situation in the future. I do not remember
what
> the dimensions were from the board edge - either before or after. But I
have
> a much higher confidence level in their design now than I had before.
>
> I'll try to find a soft copy of the "white paper" (I have it somewhere),
and
> send it to you in a separate email.
>
> Regards,
> Dale Ritzen, CQA
> Quality Manager
> Austin Manufacturing Services
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Smith, Richard
> Sent: Tuesday, January 06, 2004 7:42 AM
> To: [log in to unmask]
> Subject: [TN] Ceramic Capacitor Board Edge Clearance
>
>
> Folks,
>
> Please help by letting me know what you are using for clearance of ceramic
> capacitors to a board edge. We currently use a .160" minimum clearance on
> the edges secured by pick and place conveyor tabs and .100 (sometimes
> slightly less) to other board edges. These numbers were established for
> mechanical interference issues driven by test fixtures and pick and place.
>
> Recently, we had a problem with a couple of ceramic cap's (with a X7R
> temperature rating) that cracked near the leads after depanelizing with a
> 'pizza cutter' along the score line. It's not entirely clear to me whether
> the depaneling operation and the caps proximity to the board edge of .085"
> were the sole contributors. It seems that X7R rated caps are more prone to
> cracking and at least one manufacturers data sheet calls for .200"
clearance
> for depanelling. Modelling indicated significant stress on the component
> which decreased as the component was moved further away from the edge. Our
> solution was to route slots adjacent to the components instead of scoring
> the entire edge.
>
> As a result of this issue our Manufacturing Engineering group is asking
for
> .200" board edge clearance in our design guidelines for ALL ceramic
> capacitors. To me this seems to be overkill but, before I tell them to
> kiss-off I thought it best to find out what the rest of my fellow
designers
> are doing.
>
> Thanks Much!
>
> Rick
>
> Richard G. Smith
> CAD Services Manager
> C-COR
> "The Only Solution for Network Integrity"
> Broadband Communications Products
> 999 Research Parkway
> Meriden, Ct. 06450
> PH: 203-639-7670
> FX: 203-317-4421
> [log in to unmask]
> www.c-cor.net
>
>
>
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