Folks,

Please help by letting me know what you are using for clearance of ceramic
capacitors to a board edge. We currently use a .160" minimum clearance on
the edges secured by pick and place conveyor tabs and .100 (sometimes
slightly less) to other board edges. These numbers were established for
mechanical interference issues driven by test fixtures and pick and place.

Recently, we had a problem with a couple of ceramic cap's (with a X7R
temperature rating) that cracked near the leads after depanelizing with a
'pizza cutter' along the score line. It's not entirely clear to me whether
the depaneling operation and the caps proximity to the board edge of .085"
were the sole contributors. It seems that X7R rated caps are more prone to
cracking and at least one manufacturers data sheet calls for .200" clearance
for depanelling. Modelling indicated significant stress on the component
which decreased as the component was moved further away from the edge. Our
solution was to route slots adjacent to the components instead of scoring
the entire edge.

As a result of this issue our Manufacturing Engineering group is asking for
.200" board edge clearance in our design guidelines for ALL ceramic
capacitors. To me this seems to be overkill but, before I tell them to
kiss-off I thought it best to find out what the rest of my fellow designers
are doing.

Thanks Much!

Rick

Richard G. Smith
CAD Services Manager
C-COR
"The Only Solution for Network Integrity"
Broadband Communications Products
999 Research Parkway
Meriden, Ct. 06450
PH: 203-639-7670
FX: 203-317-4421
[log in to unmask]
www.c-cor.net



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