Hi Rex,
Were not picking on you-we understand your plight !  Our questions /
answers are more an 'educational platform' to all those that read the [DC]
forum.

 In looking at your design, it could be built as protos by companies that
specialize in the 'TOUGH'.  Here is how we would build it:
1. L3-L4: Drill, image, plate, etch, plug thru-holes, cap-plate holes
2. L2-L3-L4-L5: Laminate prepreg or RCC on both sides of L3-L4 core, laser
drill L2-L3 & L5-L4, image, plate, etch, plug blind via holes, cap-plate
holes
3. L1-L2-L5-L6: Laminate prepreg or RCC on both sides of L2-L5 core, laser
drill L1-L2 & L6-L5, image, plate, etch, solder mask, ENIG, fab

Now that I have drawn it out, this is a 2+2+2 HDI Type VI.  The big rub is
that these vias have to be stacked.  If this can be accomplished with
Staggered Vias, then this becomes a 2+2+2 HDI Type III  which is much
easier to build.  My attempts to draw this is below:

  vias:       1             2                     3                   4
L3     _________        _______       ______       _____
L4     |________|        |_______|     |______|     |_____|

 vias:       1             2                     3                   4
L2     _________       ________      ______      ______
L3     |________|       | _______|     |______|    | _____|
L4     |________| XX |_______|XX|______|XX|_____|
L5     |___________________|     |______|     |_____|

vias:       1             2                     3                   4
L1     __     ____          _______       _______________
L2     |_|__|____|         | ______|      |______________|
L3     |________|XXX| ______|XX|______|XX| _____|
L4     |________|XXX|_______|XX|_____|XX|______|
L5     |___________________|XX|_____|XX |______|
L6     |___________________________|      |______|

The Type III would look like this:
vias:       1             2                     3                   4
L1     __     ___          ______       _________________
L2     |_|__|___|       | ______|      |________________|
L3     |___________|     | ______|    |_______|     | ___|
L4     |_____|         |______|        |_____|        |_______|
L5     |____________________|      |______|    |____|
L6     |__________________________|      |_______|


Happy Holden
Westwood Associates





Rex Dalipe <[log in to unmask]>
Sent by: DesignerCouncil <[log in to unmask]>
01/23/2004 11:49 PM
Please respond to "(Designers Council Forum)"; Please respond to Rex
Dalipe


        To:     [log in to unmask]
        cc:
        Subject:        Re: [DC] Blind Vias


      Whew! I never thought my email would generate such a lot of replies.
 First of all, I would like to thank everyone for their input on the
subject matter.  This is what I love about this group - I always learn
something new everytime I open my inbox :)

      To clarify some things (before I get toasted to a crisp):

      1.) I DID NOT design this board.  Another person did it.  I was only
asked to help in finding a board manufacturer since they need the
prototype ASAP and the guy who did the board isn't in right now.

      2.) Drill size is 8 mils/0.2mm.  Yes, this would probably make the
design a whole lot more complicated

      3.) Design is for a surface mountable module - hence the size and
complexity - and why most of the bottom layer isn't usable for routing
because of the mounting pads, hence, the need for Blind vias from L1-5.
Components are all on 1 side of the board, component density is VERY HIGH
(including 2 BGAs).  I don't have the actual component/lead count but with
2 BGAs (1x48 pin and 1x144 pin both 0.8 mm pitch)  in a 1"x1" board, I
doubt that you can make anything simple.

      4.)  Layer stackup is as follows:
           TOP
           GND
           SIGNAL
           SIGNAL
           POWER
           SIGNAL
      which is the stackup which was recommended by the IC supplier who
evidently made the schematic as well.

      A couple of people have already emailed me indicating that they can
do it.  I hope that even with the additional information I provided, they
can still claim to do it :)

      Again, everyone thanks for the info.

      Regards,

      Rex Dalipe
      Design Engineer
      Eazix, I






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