First, I have to say I'm astonished Intel would let someone without
impedance experience do an impedance design for them. Lowest bidder? But
that's not your fault, as you said, they're your customer, so we do what
we can.
At first, I thought you might be describing a coplanar waveguide, a
trace embedded in a plane on the same layer, which might also reference
another plane layer. These are common in microwave design, and are
becoming more common as RF devices proliferate.
But your description of a "pair of traces" sounds just like a
differential pair, if both traces are the same width. You probably have
the calculator for that.
Finally, if you have specific guidelines from Intel regarding line
width, spacing and material, follow them. Don't worry about the
calculator.
David Ricketts
PCB Design Services
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of John Parsons
Sent: Wednesday, November 19, 2003 11:14 AM
To: [log in to unmask]
Subject: [TN] Co-planar Impedance Calculations
Greetings all,
I have a customer who is doing an impedance design for Intel and he has
no previous impedance experience. This is the information I have.
- double sided board
- target impedance 50ohm
- signal line 5mil wide, spaced 5mil from "ground" trace and this pair
of traces should be spaced a minimum of 20mil from adjacent traces.
This is what he was given from Intel. I am using an older Polar model
(CITS25 calculator) which does have models for co-planar designs but
from what I can tell they assume that the signal trace is sandwiched
between ground (return lines) on both sides. Is this a correct
interpretation? Is it possible to model the design as described above?
While we have some experience with controlled impedance I have no
experience with the aforementioned design and could use some assistance.
Best Regards
John Parsons
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