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November 2003

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Subject:
From:
Brian Ellis <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Wed, 5 Nov 2003 14:01:37 +0200
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I believe that this would depend on the CAD system being used and how it
is implemented. If we take Vutrax, for example (I cite this because it's
the one I use), there are two ways of defining the soldermask. The
default method is simply to oversize the pads on the layer by a
definable variable. For example, if a pad is 2 mm diameter (or square or
whatever shape) and the oversize is defined as 0.2 mm (or 0.080" and
0.008" respectively) the mask film would show 2.4 mm (0.096"). The
second method is to devote a layer to the mask film and to include this
in the pad stack, in which case the mask "pad" for a given stack could
be defined in any size, shape or form, irrespective of the solder pad.

Doesn't answer your question, but I believe that concurrent engineering
dictates that all the parties should sit down, round a table, and decide
on a given method and stick to it. Obviously, the method should be
compatible with the designers' CAD system, otherwise the debate becomes
futile.

Brian

David Hoover wrote:
> I am in the middle of a discussion/debate with assemblers on one side and
> designers on the other.
>
> The question is:
> What would your shop prefer to receive from the designer for soldermask
> features?
>
> either
> A) 1:1?  (Soldermask clearance same as the holesize, padsize,
> surfacemount, or
>               clearanced feature size)
> or
> B) Soldermask Clearance set at some value over the pad/feature/SMT size?
>     (Like 3 mils per side)
>
> Thanks for any and all responses,
>
> David Hoover
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