Here at PWB Interconnect Solutions Inc. we test IST coupons from many
different types of boards to determine the effects of thermal excursions on
reliability. We have found that there is a hierarchy of factors that
influence via failures. Generally speaking the single most influential
factor is plating quality and thickness, followed by the quality of
metalization (electroless or direct metalization). Secondary influences are
attributed to material followed by the rest of the fabrication variables
like hole quality, to presents of reverse etchback etc. The tertiary
influences include board design, lay-up, glass styles, copper to resin
ratios etc. The thing to realize is that the hierarchy will shift with
different aspect ratios, hole and grid sizes, total thickness, the presence
of non-functional pads and many other factors.
It must be considered that the benefits of well fabricated factors may mask
the effects of weak factors. For example good plating may mask the effects
of a poor material or bad drilling. A really good material may not stress a
poorly plated hole. But, if the plating become marginal, or the material is
exposed to excessive heat in lamination, the weak link will rise to the
surface as reduced reliability.
Without testing, coupled with cross section evaluations, it is hard to
determine degree and cause of unreliability. Some factors are intuitive,
like thin plating equates to poor performance. Other factors are not
intuitive, for example thick plating can also equate to poor performance.
The bottom line is that all fabrication variables, the material it's
physical parameters and how the material has been processed and the board
design factors; all play a role in reliability.
Recently we have been seeing an increase in blind via failures in the
industry. The failure presents itself, after assembly, as open traces that
are conductive while the board is heated but return to open or possibly
conductive with high resistance, at ambient temperatures.
Good Luck in your evaluation -
Paul Reid
Technical Projects Coordinator
PWB Inc.
-----Original Message-----
From: Rob Goodwin [mailto:[log in to unmask]]
Sent: Thursday, November 13, 2003 6:10 PM
To: [log in to unmask]
Subject: [TN] Via Reliability issues
We have been experiencing some vias not getting plated completely on several
boards out of each lot. The bare boards that come from fab pass the
connectivity and short test, but the vias don't make it through assembly.
Has anyone experienced this? Do you have any experience with a test coupon
that we could zero in on suspect boards?
Thanks,
Rob Goodwin
Eclipse Electronic Systems, Inc.
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