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November 2003

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DesignerCouncil <[log in to unmask]>
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Designers Council Forum <[log in to unmask]>, "Tempea, Ioan" <[log in to unmask]>
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Thu, 13 Nov 2003 13:45:29 -0600
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Chris Robertson <[log in to unmask]>
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Chris Robertson <[log in to unmask]>
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I have found inconsistencies of plating standards between PCB manufacturers.
You should specify both your plating thickness and the hole wall thickness.
It is understood that the hole plating is about .0002-.0003" less then the external
plating.
This ensures consistency between any manufacturer you use.
I include plating in my stack-up image/table and reference it in the notes.

I personally specify .0014" (1 oz) external plating and .0012" hole wall plating.
I also specify the hole being drilled .005" over the hole size. This is .0024 (.0012
on either side) and .0024 of solder with a solder finish with a little for +/- tolerance.

Now the trick here is if you do a SMOBC and mask over via holes, this may change.
since there will be no solder in the via hole wall. This is why some drill over only
.003-.004" over the finished size.

Now that you are armed with this information you can specify the external plating
and hole plating, avoiding hole wall cracks.

Chris Robertson
Author "PCB Designer's Reference"
[log in to unmask]
ISBN: 0130674818

  ----- Original Message -----
  From: Tempea, Ioan
  To: [log in to unmask]
  Sent: Thursday, November 13, 2003 1:17 PM
  Subject: [DC] Spec for copper thickness inside a via


  Hi,

  thanks to those who answered to my previous question on design of lead-free
  boards. This second one is actually more in your area of expertise.

  I would like to know what is the standard that specifies the copper
  thickness inside a via. We are having some protos failing after thermal
  cycling (-40 to +70) due to cracked vias.

  Thank you,
  Ioan

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