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October 2003

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Subject:
From:
David Plentovich <[log in to unmask]>
Reply To:
(Designers Council Forum)
Date:
Thu, 30 Oct 2003 20:52:36 -0500
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text/plain
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text/plain (44 lines)
David,
Normally when a clk turns into a sine wave it is becasue the capacitive load is much greater than what can be provided by the driving gate.  You would need to either change
the drive gate to one with higher current output or use several gates to drive the 32 loads.  This sounds like a bad hardware design rather than a poor layout.

Thanks, David Plentovich


David Baldwin wrote:

> I have a customer who is requesting simulation on a design that is not
> functioning that was done in OrCad.
>
> It has a 20 mhz clock with a 5ns rise time and 32 loads, but it looks like
> a sine wave.
>
> Anyone have that type of experience that would like to help them out?
>
> Thanks,
>
> Dave
>
> ___________________________________________________
> Baldwin Technologies - 1736 S. Nevada Way - Suite B
> Mesa, AZ  85204  (480) 539-4400
> http://www.baldwin-tech.com
>
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