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September 2003

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Wed, 3 Sep 2003 14:55:01 -0500
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Last Chance to REGISTER!

 

Understanding National Technology Roadmaps

September 11, 2003 ♦ Embassy Suites ♦ Napa Valley, CA

      

In an era of global competitiveness, companies are facing increasing pressure to cut costs and yet still produce innovative products. This action forces companies to take an introspective look at their capabilities, business strategies, technology needs and competitive posture in the world market. This workshop will depict key components of roadmapping and mechanisms for translating industry roadmaps into practical solutions that help a company to get ahead in this competitive market.

 

Topics Covered:

• Basic knowledge of national technology roadmapping 

• North American roadmaps 

• IPC’s national technology roadmaps 

• International technology roadmaps 

• NEMI’s national technology roadmaps 

• SIA’s international technology roadmap for semiconductors 

• The basis and purpose of roadmaps 

• Types of resources used to develop a roadmap

 

Price: $395 IPC Members         $495 nonmembers

 

To download the registration form, go to http://ipcmail.ipc.org/roadmap/roadmap_2.html, or contact Nilda Mendez at [log in to unmask] or via phone at 847-790-5329.

      

      

Bare Die Implementation

September 11, 2003 ♦ Embassy Suites ♦ Napa Valley, CA

 

The technology for mounting several bare die on an interconnecting substrate has been around for many years. Since the 1960s and 1970s, the techniques have since become pervasive in the industry, especially now in the digital age for mobile applications. This workshop will focus on die mounting technologies, tradeoff decisions; improvements in Known Good Die (KGD) processes, chip-on-board, direct chip attach technologies, wafer level packaging, and bare die integration for the module assembler.

 

Topics Covered

• Techniques for handling bare die and assembly operations

• How to specify and evaluate KGD quality from the die supplier

• Variations in mounting methods of the die in board or module assembly

• Various techniques for die interconnect (flip chip, wire bond, beam lead)

• Testing techniques for die performance and reliability of evaluations

 

Price: $395 IPC/Designer Council Members           $495 nonmembers

 

 

To download the registration form, go to http://ipcmail.ipc.org/wkshp_8/wkshp_8.html, or contact Nilda Mendez at [log in to unmask] or via phone at 847-790-5329.

 


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