Hello,

In IPC-2221, page 39, Table 6.1 is about the Electrical Conductor
Spacing. While designing a PCB with high voltage (1000 V), according to
the standart the layer-to-layer thickness and trace-to-trace clearance
is 1.5 mm (For Internal Conductors). Is this requirement is needed just
for dielectric material FR4 or for all dielectric materials table 6.1
restrictions are applicable? If not, could you please inform me about
the thickness change with the dielectric constant? And the materials for
boards with high voltage?

Actually on page 39, it is written that "When employing high voltages
and especially AC and pulsed voltages greater than 200 volts potential,
the dielectric constant and capacitive division effect of the material
must be considered in conjuction with the recommended spacing."

However there is no other information about the table 6.1. Is this table
prepared for FR4 or not?

Best Regards
Thanks in advance

Sefika Ozkal
Electronics Engineer

ASELSAN Inc.
Microelectronics, Guidance and Electro-Optics Division
Electronic Design
Address : P.O. Box:30, Etlik 06011 Ankara,TURKEY
Tel         :+90 312 847 53 00  Ext:4698
Fax       :+90 312 847 53 20
e-mail    : [log in to unmask]

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