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September 2003

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Subject:
From:
"Chezhian, Krishnan" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum.
Date:
Fri, 19 Sep 2003 15:51:22 +0800
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Hi ED,

These are my thoughts:

1. You mentioned these are via holes filled with soldermask, if that is the
case there are no component leads going into the hole & you do not have to
worry about the lead to hole ratio. In fact if the via hole is plugged the
mask will cushion the effect of z-axis expansion.

2. Since you have a tight tolerance on the outer layers with only 2 mils
annular ring after drilling, I am not sure what is the pad size you have on
the inner layers. Even though this is a 4-layer design there may not be a
significant material movement, however if the pads on the inners are tight
then the problem gets even worse.

3. If it is only an outer-layer issue, definitely it would not meet the IPC
spec. & even though it is not called for in the spec. from a reliability
point of view it would have an impact as the knee of the hole barrel is the
weakest link & subjected to the worst conditions during the pre & post
treatments during the PCB fabrication process.

4. I am not sure what is the surface finish of the boards, if it is Entek &
not covered by solder during the assembly process  then the reliability
concern is even greater.

5. However if the soldermask is not covering the surface of these pads & if
you could print solder-paste (if you are reflowing the boards)on these pads
or wavesolder them then the hole alongwith the trace will form a nice solder
fillet which will make it more reliable. If it is covered with mask & the
quantity of boards involved is high then you may want to scrape the mask on
the pad surface & get it soldered as mentioned above to make it more
reliable.

These are my thoughtsm hope it helps.

Thanks,
Krishnan

-----Original Message-----
From: Rodney Miller [mailto:[log in to unmask]]
Sent: Thursday, September 18, 2003 11:06 PM
To: [log in to unmask]
Subject: Re: [TN] Reliability question


Ed,

We have seen minimal via holes, like less than .005 annular and not had a
reliability issue.  But there are many variables still missing, like what is
your ambient operating condition and what will the joint temperature get to,
vibration, and hole to lead ratio etc.

Your biggest concern is valid with the CTE Z-axis and that the barrell of
the via may be jeapordized when the delta Temperature takes place.
Something you might consider is minimizing the hole to lead, which can be
done without major artwork change and also ensure there are pads for plating
to adhere to on the inner layers.

Bottomline however, you shouldn't worry about reliability, unless you're
warranting the work.  If that is the case, you should have ability to make
recommendations to maintain the barrel integrity, since you have little
mechanical mechanism for keeping the lead / via intact during temperature
cycling.

My $.02

Rodney

-----Original Message-----
From: Ed Berti [mailto:[log in to unmask]]
Sent: Wednesday, September 17, 2003 7:52 AM
Subject: Reliability question


I have a question concerning the reliability of a PCB that has little to no
annular ring on the via holes on the external surfaces of a multilayer
board:

-there are about 100 such holes on the board
-all components are through hole
-the board is four layers, 0.062" thick
-solder mask fills most of these via holes
-the pad size is about 0.024", with a hole drill size of 0.020", and
finished hole size of about 0.016"
-the trace coming into the hole is 0.008" wide
-there are a few locations where a trace enters a hole and there is no land
(pad) at the junction of trace/hole, just the width of the trace
-the specification is for 2 ounce copper finished amount

The board house has 100% electrically tested the boards for shorts and opens
and found no failures, and believes that the boards will be reliable. We
have assembled, wave soldered and tested (before discovery of the problem)
about 30 of the units and have found no failures related to this issue.

The boards do not meet IPC-A-600 specifications. The customer designed the
board and did not call out any IPC spec.

My concern is the long term reliability of the trace to hole junction. It
seems that I remember hearing of high density boards actually being designed
without pads: the traces came directly into the hole. Has that been done
successfully?

Is the reliability questionable? Will successful thermal cycling of the
assemblies indicate long term reliability? Any thoughts or suggestions will
be appreciated.

Thank you,

Ed Berti

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