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July 2003

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DesignerCouncil <[log in to unmask]>
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From:
"Jack C. Olson" <[log in to unmask]>
Date:
Mon, 14 Jul 2003 15:26:11 -0500
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Karl Bates <[log in to unmask]>
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"(Designers Council Forum)" <[log in to unmask]>, "Jack C. Olson" <[log in to unmask]>
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8MHz

Here's more info. We have a PowerPC processor BGA
that has many +5V and +2.6V pins. Instead of trying
to do a split plane, and having the impedance controlled
stuff possibly traveling over a split, I thought it was
better to have both a solid +5v plane and solid +2.6v
planes on different layers. But as soon as you do that,
you have some signals closer to one plane that the other,
and the question is will there be signal integrity issues
by using the +5v plane as a reference.

On the other hand, how do you guys create complicated
split planes and keep signals from crossing the split?
(Veribest/Mentor Expedition/Mentor BoardStationRE
router)

thanks,
Jack





                      Karl Bates
                      <[log in to unmask]
                      >
                      Sent by:
                      DesignerCouncil         To: [log in to unmask]
                      <DesignerCouncil@listse cc:
                      rv.ipc.org>


                      07/14/2003 02:10 PM       Subject:      Re: [DC] Reference Planes for Impedance Controlled Signals
                      Please respond to
                      "(Designers Council
                      Forum)"; Please respond
                      to Karl Bates





Caterpillar: Confidential Green                 Retain Until: 08/13/2003
                                                Retention Category:  G90 -
                                                General
                                                Matters/Administration




And...What frequency is the circuit operating at ?    Khz or Mhz or Ghz ?

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