Hmmm...
I'm not sure which question you asked last year, but I will attempt both
answers.
Maybe this is your lucky day! <grin>
Thermal Relief Web Width:
It sounds like you are saying you use two different CAD systems; in one you
can only specify a single web width that is applied to every thermal
relief, and in the other you can specify different widths for different pad
sizes. Is that right? Anyway, The idea behind having a thermal relief in
the first place is that if you are applying heat to the pad, you don't want
the heat to dissipate into the plane before it has a chance to melt the
solder, right? Well, a lot of boards are reflow soldered (in an oven) which
melts everything, and the boards are seldom if ever reworked, so it doesn't
make a lot of difference what exact width is used .The no-brainer way to
assign them (what I've seen at most of the companies I've worked at) is to
choose the typical trace width. The majority of designs I've seen, if the
trace width is 8 mils the web width is 8 mils. Not that it is best, just
typical.
This is NOT the way IPC recommends they be calculated. If you are doing a
lot of hand-soldering or just have a passion for doing things the
scientific way, IPC recommends that you base the web width as a percentage
of the size of pad, I guess they figure if you are soldering a big hole you
will apply more heat anyway to melt big ol' fat leads. I'm curious about
the common sense thought that if a person is sitting at a bench with a
typical soldering iron doing lots of soldering using about the same dwell
time, the webs should be about the same. After all, you are trying to hold
the same amount of heat in no matter where you are touching the board. It
almost makes sense to use smaller webs on a huge pad because you are trying
to heat up a larger area with the same tip, you don't need the heat to
escape at all! Any physics professors out there care to comment?
Anyway, if you use small pads and do the calculation and divide by the
number of webs (4?) you come up with like 3mils sometimes? no thanks... My
system lets me pick one size web for each plane or area-fill which is kind
of a compromise between your two situations. Usually I'm more concerned
with current requirements, add the possibility of having two or more planes
in the same stackup (how about ten impedance control reference planes?) and
the calculation kind of goes out the window.
Fab Tolerance:
No, the Hole Location Tolerance is different. The Manufacturing Allowance
(I always call it Fab Tolerance) is a strange value. Nothing is perfect,
your boards are never perfect. So try and figure out every way a board can
get screwed up; a couple of mils off transferring data to an image (film?),
lose some more transferring the image to the material, humidity and
temperature changes take some more, stacking the layers up imperfectly cost
some more, drilling is off some more... and on and on. If you add up all
the ways something can go wrong it seems miraculous that high-tech boards
ever work. Well, instead of adding it up there is some mathematical
statistical formula called "sum of the squares" or something goofy like
that, and the end result is that you only have to give a really really good
vendor an "allowance" of like 7.9mils(?) but if you have a design that
anyone can make cheaply you need to allow something easy, like double that.
You also add more if the design is more than 8 layers or larger than 12
inches (they might have discarded the 12inch deal can't remember) but
anyway, once you get used to it, you can use certain features sizes knowing
you are doing a "level b" design (for example) and know that the
calculations for appropriate pad sizes and stuff like that has taken the
allowance into account. For example, if you do tight designs and use
leading edge vendors, you can calculate a pad size for a 20mil hole as
maxhole+2minannularing+fabtol=20+2+7.97=<30 but if you use a garage shop
you have to design to level a which is 20+2+16=38, quite a big difference
well, its gettin' late...
hope that helped,
Jack
Lum Wee Mei
<[log in to unmask]>
Sent by:
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<DesignerCouncil@listse To: [log in to unmask]
rv.ipc.org> cc:
06/25/2003 07:31 PM
Please respond to Subject: Re: [DC] Thermal Relief Calculations
"(Designers Council
Forum)"; Please respond
to Lum Wee Mei
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General
Matters/Administration
Mark,
You have asked the same question I did last year. No one has attempted
to answer me. I wish you luck this time and hoping to bank on your luck,
someone will be kind enough to give us a good explanation?
Regards,
Wee Mei
Mark Holmes wrote:
>Hi all,
>
>I am looking at IPC-2222 9.1.2 regarding thermal relief pads. It provides
a
>formula for
>the web width based on the minimum pad size.
>
>I can use this method with my current software, which allows me to create
a
>thermal
>relief for each pad. But, I also use a system that only allows me to
specify
>thermal
>relief pads for 'non-vias' in a particular plane.
>
>My questions are, what are you guys using to calculate your thermal relief
>pads?
>Do you calculate the web size for each pad used, Or do you have some other
>method of calculating the web width.
>
>Any advice, rules of thumb etc. would be most appreciated.
>
>Just one more thing, could anyone confirm what is meant by "Standard
>Manufacturing Allowance"
>in IPC-2222 Figure 9-1. Is this the same as IPC-2221 table 9-3 "Minimum
Hole
>Location Tolerance, dtp"?
>
>Regards.
>
>Mark
>
>Mark Holmes PCB Designer
>Helvar Merca Ltd.
>Hawley Mill
>Hawley Road
>Dartford
>Kent DA2 7SY
>Tel: 01322 222211
>mailto:[log in to unmask]
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